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    Wyświetlanie 1-5 z 5
    Tytuł:
    Residue number system (RNS)
    Autorzy:
    Sharoun, A. O.
    Powiązania:
    https://bibliotekanauki.pl/articles/376029.pdf
    Data publikacji:
    2013
    Wydawca:
    Politechnika Poznańska. Wydawnictwo Politechniki Poznańskiej
    Tematy:
    residue number system
    RNS
    residue arithmetic
    Opis:
    In the residue number system, a set of moduli which are independent of each other is given. An integer is represented by the residue of each modulus and the arithmetic operations are based on the residues individually. The arithmetic operations based on residue number system can be performed on various moduli independently to avoid the carry in addition, subtraction and multiplication, which is usually time consuming. However, the comparison and division are more complicated and the fraction number computation is immatured. Due to this, a residue number system is not yet popular in general-purpose computers, though it is extremely useful for digital-signal-processing applications. This thesis deals with the design, simulation and microcontroller implementation of some (residue number system based) building blocks for applications in the field of digital signal processing. The building blocks which have been studied are binary to residue converter, residue to binary converter, residue adder and residue multiplier.
    Źródło:
    Poznan University of Technology Academic Journals. Electrical Engineering; 2013, 76; 265-270
    1897-0737
    Pojawia się w:
    Poznan University of Technology Academic Journals. Electrical Engineering
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Pipelined division of signed numbers with the use of residue arithmetic for small number range with the programmable gate array
    Autorzy:
    Smyk, R.
    Ulman, Z.
    Czyżak, M.
    Powiązania:
    https://bibliotekanauki.pl/articles/376378.pdf
    Data publikacji:
    2013
    Wydawca:
    Politechnika Poznańska. Wydawnictwo Politechniki Poznańskiej
    Tematy:
    pipelining
    residue number system
    RNS
    residue arithmetic
    Opis:
    In this work an architecture of the pipelined signed residue divider for the small number range is presented. Its operation is based on reciprocal calculation and multiplication by the dividend. The divisor in the signed binary form is used to compute the approximated reciprocal in the residue form by the table look-up. In order to limit the look-up table address an algoritm based on segmentation of the divisor into two segments is used. The approximate reciprocal transformed to residue representation with the proper sign is stored in look-up tables. During operation it is multiplied by the dividend in the residue form and subsequently scaled. The pipelined realization of the divider in the FPGA environment is also shown.
    Źródło:
    Poznan University of Technology Academic Journals. Electrical Engineering; 2013, 76; 117-126
    1897-0737
    Pojawia się w:
    Poznan University of Technology Academic Journals. Electrical Engineering
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Scaling of signed residue numbers with mixed-radix conversion in FPGA with extended scaling factor selection
    Autorzy:
    Smyk, R.
    Czyżak, M.
    Ulman, Z.
    Powiązania:
    https://bibliotekanauki.pl/articles/97226.pdf
    Data publikacji:
    2013
    Wydawca:
    Politechnika Poznańska. Wydawnictwo Politechniki Poznańskiej
    Tematy:
    residue number system
    RNS
    scaling
    scaling algorithms
    mixed-radix system
    MRS
    FPGA
    Opis:
    A scaling technique of signed residue numbers in FPGA is proposed. The technique is based on conversion of residue numbers to the Mixed-Radix System (MRS). The scaling factor is assumed to be a moduli product from the Residue Number System (RNS) base. Scaling is performed by scaling of MRS terms, the subsequent generation of residue representations of scaled terms, binary addition of these representations and generation of residues for all moduli. The sign of the residue number is detected by using the most significant digit of the MRS representation. Basic blocks of the scaler are realized in the form of modified two-operand modulo adders with included additional multiply and modulo reduction operations. An exemplary pipelined realization of the scaler in the Xilinx FPGA environment is shown. The design is based on Look-Up Tables (LUT)(2,sup>6 x 1) that simulate small RAMs which serve as main components for the look-up realization. Also a method is shown that allows for flexible selection of scaling factors from a set of moduli products of the RNS base. This is made by forming auxiliary MRSs by permutation of moduli of the base. All formed MRSs are associated with the given RNS with respect to the base but each MRS has different set of weights. Thus for the required scaling factor, the suitable MRS can be chosen that provides for the scaling error smaller than 1.
    Źródło:
    Computer Applications in Electrical Engineering; 2013, 11; 465-477
    1508-4248
    Pojawia się w:
    Computer Applications in Electrical Engineering
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Scaling of numbers in residue arithmetic with the flexible selection of scaling factor
    Autorzy:
    Ulman, Z.
    Czyżak, M.
    Smyk, R.
    Powiązania:
    https://bibliotekanauki.pl/articles/376813.pdf
    Data publikacji:
    2013
    Wydawca:
    Politechnika Poznańska. Wydawnictwo Politechniki Poznańskiej
    Tematy:
    scaling technique
    scaling factor
    residue arithmetic
    Residue Number System
    RNS
    Mixed-Radix System
    MRS
    Opis:
    A scaling technique of numbers in residue arithmetic with the flexible selection of the scaling factor is presented. The required scaling factor can be selected from the set of moduli products of the Residue Number System (RNS) base. By permutation of moduli of the number system base it is possible to create many auxiliary Mixed-Radix Systems (MRS). They serve as the intermediate systems in the scaling process. All MRS's are associated with the given RNS with respect to the base, but they have different sets of weights. For the scaling factor value resulting from the requirements of the given signal processing algorithm, the suitable MRS can be chosen that allows to obtain the scaling result in most simple manner.
    Źródło:
    Poznan University of Technology Academic Journals. Electrical Engineering; 2013, 76; 175-179
    1897-0737
    Pojawia się w:
    Poznan University of Technology Academic Journals. Electrical Engineering
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    RNS/TCS converter design using high-level synthesis in FPGA
    Wysokopoziomowa synteza konwertera RNS/U2 w FPGA
    Autorzy:
    Smyk, R.
    Czyżak, M.
    Powiązania:
    https://bibliotekanauki.pl/articles/269200.pdf
    Data publikacji:
    2017
    Wydawca:
    Politechnika Gdańska. Wydział Elektrotechniki i Automatyki
    Tematy:
    Residue Number System
    RNS
    two's-complement system
    TCS
    Chinese Remainder Theorem I
    CRT I
    FPGA
    system resztowy
    system z uzupełnieniem do 2
    U2
    konwerter RNS/U2
    chińskie twierdzenie o resztach
    Opis:
    An experimental high-level synthesis (HLS) of the residue number system (RNS) to two’s-complement system (TCS) converter in the Vivado Xilinx FPGA environment is shown. The assumed approach makes use of the Chinese Remainder Theorem I (CRT I). The HLS simplifies and accelerates the design and implementation process, moreover the HLS synthesized architecture requires less hardware by about 20% but the operational frequency is smaller by 30% than that for the VHDL designed converter.
    W pracy przedstawiono eksperymentalną wysokopoziomową syntezę w FPGA konwertera L systemu resztowego do systemu reprezentacji z uzupełnieniem do 2 (U2). W zastosowanym podejściu wykorzystano algorytm konwersji na bazie chińskiego twierdzenia o resztach (CRT 1), Zauważono, że synteza wysokopoziomowa ułatwia proces projektowania oraz zauważalnie skraca czas testowania układu. Zaprojektowana architektura konwertera przy wykorzystaniu syntezy wysokopoziomowej pochłania o około 20% zasobów układu FPGA mniej niż dla konwertera zaprojektowanego przy użyciu języka VHDL, jednak maksymalna częstotliwość pracy jest niższa o około 30%.
    Źródło:
    Zeszyty Naukowe Wydziału Elektrotechniki i Automatyki Politechniki Gdańskiej; 2017, 57; 121-126
    1425-5766
    2353-1290
    Pojawia się w:
    Zeszyty Naukowe Wydziału Elektrotechniki i Automatyki Politechniki Gdańskiej
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-5 z 5

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