Temat: pipelining - Katalog OPAC zbiorów

Skocz do pozycji: 1.

Tytuł:: Low-cost hardware implementations of Salsa20 stream cipher in programmable devices
Autorzy:: Sugier, J.
Powiązania:: https://bibliotekanauki.pl/articles/2069359.pdf
Data publikacji:: 2013
Wydawca:: Uniwersytet Morski w Gdyni. Polskie Towarzystwo Bezpieczeństwa i Niezawodności
Tematy:: FPGA
stream cipher
hardware implementation
pipelining
iterative architecture
Opis:: Salsa20 is a 256-bit stream cipher that has been proposed to eSTREAM, ECRYPT Stream Cipher Project, and is considered to be one of the most secure and relatively fastest proposals. This paper describes hardware implementation of various architectures of this cipher in popular Field Programmable Gate Arrays (FPGA). The implemented architectures are based on the loop-unrolled data flow organization and after pipelining they can reach the throughput in the range of 20 – 30 Gbps even after fully automatic implementation in popular low-cost families of Spartan-3 and Spartan-6 from Xilinx. More resource-limited iterative architectures achieve speed of 1 – 2 Gbps. The results that are included in this work present potential of the algorithm when it is implemented in a specific FPGA environment and provide some information for evaluation of cipher effectiveness in contemporary popular programmable devices.
Źródło:: Journal of Polish Safety and Reliability Association; 2013, 4, 1; 121--128
2084-5316
Pojawia się w:: Journal of Polish Safety and Reliability Association
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 2.

Tytuł:: Efficiency of FPGA architectures in implementations of AES, Salsa20 and Keccak cryptographic algorithms
Autorzy:: Sugier, J.
Powiązania:: https://bibliotekanauki.pl/articles/2069086.pdf
Data publikacji:: 2015
Wydawca:: Uniwersytet Morski w Gdyni. Polskie Towarzystwo Bezpieczeństwa i Niezawodności
Tematy:: block cipher
hash function
hardware implementation
loop unrolling
pipelining
FPGA
Opis:: The aim of this paper is to test efficiency of automatic implementation of selected cryptographic algorithms in two families of popular-grade FPGA devices from Xilinx: Spartan-3 and Spartan-6. The set of algorithms include the Advanced Encryption Standard (AES) used worldwide as a symmetric cipher along with two hash algorithms: Salsa20 (developed with ECRYPT Stream Cipher Project) and Keccak permutation function (core of the new SHA-3 standard). The ciphers were expressed in 5 architectures: the basic iterative one (one instance of a round in hardware) and its four derivatives created by loop unrolling and pipelining. With each of the architectures implemented in both Spartan devices this gave the total of 30 test cases, which, upon automatic implementation, created a comprehensive and consistent base for comparison of the ciphers, applied architectures and FPGA devices used for implementation.
Źródło:: Journal of Polish Safety and Reliability Association; 2015, 6, 2; 117--124
2084-5316
Pojawia się w:: Journal of Polish Safety and Reliability Association
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 3.

Tytuł:: Implementing SHA-3 candidate BLAKE algorithm in Field Programmable Gate Arrays
Autorzy:: Sugier, J.
Powiązania:: https://bibliotekanauki.pl/articles/2069234.pdf
Data publikacji:: 2016
Wydawca:: Uniwersytet Morski w Gdyni. Polskie Towarzystwo Bezpieczeństwa i Niezawodności
Tematy:: BLAKE algorithm
FPGA
hash function
implementation efficiency
loop unrolling
pipelining
Opis:: BLAKE is a cryptographic hash function proposed as a candidate in SHA-3 contest where he successfully qualified to the final round with other 4 candidates. Although it eventually lost to KECCAK it is still considered as a suitable solution with good cryptographic strength and great performance especially in software realizations. For these advantages BLAKE is commonly selected to be a hash function of choice in many contemporary IT systems in applications like digital signatures or message authentication. The purpose of this paper is to evaluate how the algorithm is suitable to be implemented in hardware using low-cost Field Programmable Gate Array (FPGA) devices, particularly to test how efficiently its complex internal transformations can be realized with FPGA resources when overall size of the implementation grows substantially with multiple rounds of the cipher running in parallel in hardware and capacity of the configurable array is used up to its limits. The study was made using the set of 7 different architectures with different loop unrolling factors and with optional application of pipelining, with each architecture being implemented in two popular families of FPGA devices from Xilinx. Investigation of the internal characteristic of the implementations generated by the tools helped in analysis how the fundamental mechanism of loop unrolling with or without pipelining works in case of this particular cipher.
Źródło:: Journal of Polish Safety and Reliability Association; 2016, 7, 1; 193--200
2084-5316
Pojawia się w:: Journal of Polish Safety and Reliability Association
Dostawca treści:: Biblioteka Nauki

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