- Tytuł:
- FPGA implementations of low precision floating point multiply-accumulate
- Autorzy:
-
Amaricai, A.
Boncalo, O.
Sicoe, O - Powiązania:
- https://bibliotekanauki.pl/articles/397897.pdf
- Data publikacji:
- 2013
- Wydawca:
- Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
- Tematy:
-
digital arithmetic
floating point arithmetic
FPGA
field programmable gate array (FPGA)
multiply-accumulate
dot product
arytmetyka cyfrowa
arytmetyka zmiennoprzecinkowa
field-programmable gate array
MAC
iloczyn skalarny - Opis:
- Floating point (FP) multiply-accumulate (MAC) represents one of the most important operations in a wide range of applications, such as DSP, multimedia or graphic processing. This paper presents a FP MAC half precision (16-bit) FPGA implementation. The main contribution of this work is represented by the utilization of modern FPGA DSP block for performing both mantissa multiplication and mantissa accumulation. In order to use the DSP block for these operations, the alignment right shifts are performed before the multiply-add stage: a right shift on one of the multiplicand, and, a left shift for the other. This results in efficient DSP usage; thus both cost savings and higher performance (high working frequencies and low latencies) are targeted for MAC operations.
- Źródło:
-
International Journal of Microelectronics and Computer Science; 2013, 4, 4; 159-163
2080-8755
2353-9607 - Pojawia się w:
- International Journal of Microelectronics and Computer Science
- Dostawca treści:
- Biblioteka Nauki
Artykuł