- Tytuł:
- The use of hierarchical structures for design of high-speed digital comparators on FPGA/SoC
- Autorzy:
- Salauyou, V.
- Powiązania:
- https://bibliotekanauki.pl/articles/114377.pdf
- Data publikacji:
- 2016
- Wydawca:
- Stowarzyszenie Inżynierów i Techników Mechaników Polskich
- Tematy:
-
comparator
high-speed
hierarchical structures
system on chip
field programmable logic array
FPGA
SoC - Opis:
- This paper presents a design method of high-speed digital comparators on FPGA/SoC by means of hierarchical structures. A synthesis technique of hierarchical structures for comparators is offered. In this technique, the comparator best hierarchical structure is empirically found for a certain FPGA family. The proposed method allows reducing a delay for 256-bits comparators by 1.245 to 2.516 times as compared with a traditional approach, and for 512-bits comparators by 3.399 times. The method also allows reducing an area by 40.2% on occasion.
- Źródło:
-
Measurement Automation Monitoring; 2016, 62, 6; 196-198
2450-2855 - Pojawia się w:
- Measurement Automation Monitoring
- Dostawca treści:
- Biblioteka Nauki
Artykuł