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    Wyświetlanie 1-3 z 3
    Tytuł:
    Design of a nanoswitch in 130 nm CMOS technology for 2.4 GHz wireless terminals
    Autorzy:
    Bhuiyan, M. A.
    Reaz, M. B. I.
    Jalil, J.
    Rahman, L. F.
    Powiązania:
    https://bibliotekanauki.pl/articles/200508.pdf
    Data publikacji:
    2014
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    CMOS
    ISM band
    nanometer
    transceivers
    T/R switch
    wireless
    Opis:
    This paper proposes a transmit/receive (T/R) nanoswitch in 130 nm CMOS technology for 2.4 GHz ISM band transceivers. It exhibits 1.03-dB insertion loss, 27.57-dB isolation and a power handling capacity (P1 dB) of 36.2-dBm. It dissipates only 6.87 μW power for 1.8/0 V control voltages and is capable of switching in 416.61 ps. Besides insertion loss and isolation of the nanoswitch is found to vary by 0.1 dB and 0.9 dB, respectively for a temperature change of 125°C. Only the transistor W/L optimization and resistive body floating technique is used for such lucrative performances. Besides absence of bulky inductors and capacitors in the schematic circuit help to attain the smallest chip area of 0.0071 mm2 which is the lowest ever reported in this frequency band. Therefore, simplicity and low chip area of the circuit trim down the cost of fabrication without compromising the performance issue.
    Źródło:
    Bulletin of the Polish Academy of Sciences. Technical Sciences; 2014, 62, 2; 399-406
    0239-7528
    Pojawia się w:
    Bulletin of the Polish Academy of Sciences. Technical Sciences
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    On-chip current-mode approach to thwart CPA attacks in CMOS nanometer technology
    Autorzy:
    Bellizia, D.
    Scotti, G.
    Trifiletti, A.
    Powiązania:
    https://bibliotekanauki.pl/articles/398086.pdf
    Data publikacji:
    2016
    Wydawca:
    Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
    Tematy:
    IoT
    internet of things (IoT)
    Power Analysis Attacks
    smart card
    CPA
    current-mode
    Side Channel Analysis
    CMOS
    Cryptography
    PRESENT
    Internet rzeczy
    karta inteligentna
    moduły prądowe
    kryptografia
    Opis:
    The protection of information that reside in smart devices like IoT nodes is becoming one of the main concern in modern design. The possibility to mount a non-invasive attack with no expensive equipment, such as a Power Analysis Attack (PAA), remarks the needs of countermeasures that aims to thwart attacks exploiting power consumption. In addition to that, designers have to deal with demanding requirements, since those smart devices require stringent area and energy constraints. In this work, a novel analog-level approach to counteract PAA is presented, taking benefits of the current-mode approach. The kernel of this approach is that the information leakage exploited in a PAA is leaked through current absorption of a cryptographic device. Thanks to an on-chip measuring of the current absorbed by the cryptographic logic, it is possible to generate an error signal. Throughout a current-mode feedback mechanism, the data-dependent component of the overall consumption can be compensated, making the energy requirement constant at any cycle and thwarting the possibility to recover sensible information. Two possible implementations of the proposed approach are presented in this work and their effectiveness has been evaluated using a 40nm CMOS design library. The proposed approach is able to increase the Measurements to Disclosure (MTD) of at least three orders of magnitude, comparing to the unprotected implementation. It has to be pointed out that the on-chip current-mode suppressor, based on the proposed approach, is able to provide a very good security performance, while requiring a very small overhead in terms of silicon area (xl.007) and power consumption (xl.07).
    Źródło:
    International Journal of Microelectronics and Computer Science; 2016, 7, 4; 147-156
    2080-8755
    2353-9607
    Pojawia się w:
    International Journal of Microelectronics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Applying shallow nitrogen implantation from rf plasma for dual gate oxide technology
    Autorzy:
    Bieniek, T.
    Beck, R. B.
    Jakubowski, A.
    Głuszko, G.
    Konarski, P.
    Ćwil, M.
    Powiązania:
    https://bibliotekanauki.pl/articles/308685.pdf
    Data publikacji:
    2007
    Wydawca:
    Instytut Łączności - Państwowy Instytut Badawczy
    Tematy:
    CMOS
    dual gate oxide
    gate stack
    oxynitride
    plasma implantation
    Opis:
    The goal of this work was to study nitrogen implantation from plasma with the aim of applying it in dual gate oxide technology and to examine the influence of the rf power of plasma and that of oxidation type. The obtained structures were examined by means of ellipsometry, SIMS and electrical characterization methods.
    Źródło:
    Journal of Telecommunications and Information Technology; 2007, 3; 3-8
    1509-4553
    1899-8852
    Pojawia się w:
    Journal of Telecommunications and Information Technology
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-3 z 3

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