Temat: ultra low power - Katalog OPAC zbiorów

Skocz do pozycji: 1.

Tytuł:: Double-gate MOSFET Model Implemented in Verilog-AMS Language for the Transient Simulation and the Configuration of Ultra Low-power Analog Circuits
Autorzy:: Smaani, Billel
Meraihi, Yacin
Nafa, Fares
Benlatreche, Mohamed Salah
Akroum, Hamza
Latreche, Saida
Powiązania:: https://bibliotekanauki.pl/articles/2055208.pdf
Data publikacji:: 2021
Wydawca:: Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:: double-gate MOSFET
compact model
ultra low power analog circuits
Opis:: This paper deals with the implementation of a DC and AC double-gate MOSFET compact model in the Verilog-AMS language for the transient simulation and the configuration of ultra low-power analog circuits. The Verilog-AMS description of the proposed model is inserted in SMASH circuit simulator for the transient simulation and the configuration of the Colpitts oscillator, the common-source amplifier, and the inverter. The proposed model has the advantages of being simple and compact. It was validated using TCAD simulation results of the same transistor realized with Silvaco Software.
Źródło:: International Journal of Electronics and Telecommunications; 2021, 67, 4; 609--614
2300-1933
Pojawia się w:: International Journal of Electronics and Telecommunications
Dostawca treści:: Biblioteka Nauki

Artykuł

Skocz do pozycji: 2.

Tytuł:: Design of an Ultra-Low Power CT Σ∆ A/D Modulator in 65nm CMOS for Cardiac Pacemakers: From System Synthesis to Circuit Implementation
Autorzy:: Wang, Y.
Cai, H.
Powiązania:: https://bibliotekanauki.pl/articles/226202.pdf
Data publikacji:: 2014
Wydawca:: Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:: cardiac pacemaker
CMOS
ultra-low power
analogue-to-digital
Sigma-Delta modulation
continuous-time
Opis:: A high performance, ultra-low power, fully differentia 2nd-order continuous-time Σ∆ analogue-to-digital modulator for cardiac pacemakers is presented in this paper. The entire design procedure is described in detail from the high-level system synthesis in both discrete and continuous-time domain, to the low-level circuit implementation of key functional blocks of the modulator. The power consumption of the designed modulator is rated at 182nA from a 1.2V power supply, meeting the ultra-low power requirement of the cardiac pacemaker applications. A 65nm CMOS technology is employed to implement the Σ∆ modulator. The modulator achieves a simulated SNR of 53.8dB over a 400 Hz signal bandwidth, with 32KHz sampling frequency and an oversampling ratio of 40. The active area of the modulator is 0.45×0.50mm².
Źródło:: International Journal of Electronics and Telecommunications; 2014, 60, 1; 109-115
2300-1933
Pojawia się w:: International Journal of Electronics and Telecommunications
Dostawca treści:: Biblioteka Nauki

Artykuł

Skocz do pozycji: 3.

Tytuł:: Ultra Low Power Design for Digital CMOS Circuits Operating Near Threshold
Autorzy:: Kalra, S.
Bhattacharyya, A. B.
Powiązania:: https://bibliotekanauki.pl/articles/226500.pdf
Data publikacji:: 2017
Wydawca:: Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:: energy efficiency
ultra-low power
EKV
minimum energy point
minimum delay point temperature to time generator
Opis:: Circuits operating in the subthreshold region are synonymous to low energy operation. However, the penalty in performance is colossal. In this paper, we investigate how designing in moderate inversion region recuperates some of that lost performance, while remaining very near to the minimum energy point. An α power based minimum energy delay modeling that is continuous over the weak, moderate, and strong inversion regions is presented. The value of α is obtained through interpolation following EKV model. The effect of supply voltage and device sizing on the minimum energy and performance is determined. The proposed model is utilized to design a temperature to time generator at 32nm technology node as the application of the proposed model. The abstract goes here.
Źródło:: International Journal of Electronics and Telecommunications; 2017, 63, 4; 369-374
2300-1933
Pojawia się w:: International Journal of Electronics and Telecommunications
Dostawca treści:: Biblioteka Nauki

Artykuł

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