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Wyświetlanie 1-15 z 101
Tytuł:
On Transformation of a Logical Circuit to a Circuit with NAND and NOR Gates Only
Autorzy:
Baranov, S.
Karatkevich, A.
Powiązania:
https://bibliotekanauki.pl/articles/963932.pdf
Data publikacji:
2018
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
logic synthesis
logic devices
VLSI
minimization
Opis:
In the paper we consider fast transformation of a multilevel and multioutput circuit with AND, OR and NOT gates into a functionally equivalent circuit with NAND and NOR gates. The task can be solved by replacing AND and OR gates by NAND or NOR gates, which requires in some cases introducing the additional inverters or splitting the gates. In the paper the quick approximation algorithms of the circuit transformation are proposed, minimizing number of the inverters. The presented algorithms allow transformation of any multilevel circuit into a circuit being a combination of NOR gates, NAND gates or both types of universal gates.
Źródło:
International Journal of Electronics and Telecommunications; 2018, 64, 3; 373-378
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
High-Performance Ternary (4:2) Compressor Based on Capacitive Threshold Logic
Autorzy:
Mirzaee, R. F.
Reza, A.
Powiązania:
https://bibliotekanauki.pl/articles/225977.pdf
Data publikacji:
2017
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
4:2 compressor
ternary logic
multiple-valued logic
CNFET
threshold logic
Opis:
This paper presents a ternary (4:2) compressor, which is an important component in multiplication. However, the structure differs from the binary counterpart since the ternary model does not require carry signals. The method of capacitive threshold logic (CTL) is used to achieve the output signals directly. Unlike the previously presented similar structure, the entire capacitor network is divided into two parts. This segregation results in higher reliability and robustness against unwanted process, voltage, and temperature (PVT) variations. Simulations are performed by HSPICE and 32nm CNFET technology. Simulation results demonstrate about 94% higher performance in terms of power-delay product (PDP) for the new design over the previous one.
Źródło:
International Journal of Electronics and Telecommunications; 2017, 63, 4; 355-361
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Experimental Comparison of Synthesis Tools Altera Quartus II and Synthagate
Autorzy:
Węgrzyn, M.
Karatkevich, A.
Powiązania:
https://bibliotekanauki.pl/articles/226665.pdf
Data publikacji:
2013
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
logic design
state machines
logic devices
FPGA
VHDL
Opis:
The paper presents comparison between efficiency of an industrial FPGA design software tool Altera Quartus II and similar design software tool Synthagate by Syntezza company of an academic origin. The experiments were performed using a series of examples describing the Mealy finite state machines; onehot state encoding was used in all cases. Area (number of used logical blocks) was the main parameter used for the comparison. Influence of the way of FSM description (in VHDL language) on the quality of synthesis was studied. The obtained results show that Synthagate in almost all cases performs synthesis more efficiently and essentially quicker than Altera Quartus. Section I presents motivation of the research. Section II reminds the notion of FSM. Section III describes problems which had to be solved to provide correctness of experimental comparison. Section IV presents some details about state encoding way used in the experiments. In Section V, the experimental results are presented. Section VI describes the problems related to the comparison which still have to be solved. Section VII presents the conclusions from the experiments. Section VIII suggests possible reasons of the detected situation.
Źródło:
International Journal of Electronics and Telecommunications; 2013, 59, 4; 357-362
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Application of Indexed Partition Calculus in Logic Synthesis of Boolean Functions for FPGAs
Autorzy:
Rawski, M.
Powiązania:
https://bibliotekanauki.pl/articles/226483.pdf
Data publikacji:
2011
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
indexed partition
logic synthesis
FPGA
Opis:
Functional decomposition of Boolean functions specified by cubes proved to be very efficient. Most popular decomposition methods are based on blanket calculus. However computation complexity of blanket manipulations strongly depends on number of function's variables, which prevents them from being used for large functions of many input and output variables. In this paper a new concept of indexed partition is proposed and basic operations on indexed partitions are defined. Application of this concept to logic synthesis based on functional decomposition is also discussed. The experimental results show that algorithms based on new concept are able to deliver good quality solutions even for large functions and does it many times faster than the algorithms based on blanket calculus.
Źródło:
International Journal of Electronics and Telecommunications; 2011, 57, 2; 209-216
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Measures for evaluation of structure and semantics of ontologies
Autorzy:
Waloszek, W.
Powiązania:
https://bibliotekanauki.pl/articles/220653.pdf
Data publikacji:
2012
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
ontology
description logic
Knowledge Cartography
Opis:
Recently, the topic of ontologies has growing attention from the IT community. Various processes of ontology creation, integration, and deployment have been proposed. As a consequence there appeared an urgent need for evaluating the resulting ontologies in a quantitative way. A number of metrics has been defined along with different approaches to measuring the properties of ontologies. In the first part of this paper we review the state of the art in this domain. Special attention is devoted to discussing differences between syntactic measures (referring to various properties of graphs that represent ontologies) and semantic measures (reflecting the properties of the space of ontology models). In the second part we propose an alternative approach to quantification of semantics of an ontology. The original proposal presented here exploits specific methods of representing the space of semantic models used for optimization of reasoning. We argue that this approach enables us to capture different kinds of relations among ontology terms and offers possibilities of devising new useful measures.
Źródło:
Metrology and Measurement Systems; 2012, 19, 2; 343-354
0860-8229
Pojawia się w:
Metrology and Measurement Systems
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
The railway operation process evaluation method in terms of resilience analysis
Autorzy:
Restel, Franciszek
Powiązania:
https://bibliotekanauki.pl/articles/1833611.pdf
Data publikacji:
2021
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
railway
resilience
performance
Fuzzy Logic
Opis:
In complex socio-technical systems there is an influence of safe unwanted events on the occurrence of accidents. It is like domino bricks. Therefore, it is not only the recovery from major events that is important, but also the recovery from disruptions in operation. As the literature review shows, the recovery of operation processes is analysed by single criterions for small disruptions. On the other hand, resilience research is focused on the network and major events, but not on frequent small-consequence events that affect operational processes. The performance of a system is a key parameter when evaluating resilience. As a result of the performed literature survey, the aim of the paper was to propose a new method for evaluating performance in terms of operational processes and resilience analysis. Moreover, it is also important to order the most important terms related to this issue, as well as to introduce new types of qualities, which are not only focused on the system, but also on the implemented operational processes. The paper consists of eight sections. The introduction section describes generally the problem, that leads to formulation of the aim of the paper and description of its structure. It is followed by the second section consisting of a complex literature survey. Section three orders the reliability, robustness and resilience definitions. Section four analyses the performance influencing factors using Fault and Event Tree Analysis, while section five defines the operational layer of the system and shows a formal description of operation processes. Section six presents the operation process evaluation model. It was elaborated using the Fuzzy Logic approach, that allows combining of incoherent system and process qualities: punctuality, probability no further delays, quantitative implementation of scheduled processes, reconfiguration level. Afterwards a case study is shown to present the method application. The performed case study shows the advantages of the proposed approach, which is related to the most common methods. The paper ends with conclusions and further research perspectives.
Źródło:
Archives of Transport; 2021, 57, 1; 73-89
0866-9546
2300-8830
Pojawia się w:
Archives of Transport
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Analysis of High-Performance Near-threshold Dual Mode Logic Design
Autorzy:
Bikki, Pavankumar
Powiązania:
https://bibliotekanauki.pl/articles/226748.pdf
Data publikacji:
2019
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
CMOS logic
dual mode logic
dynamic mode
high performance
minimum energy point
near-threshold
Opis:
A novel dual mode logic (DML) model has a superior energy-performance compare to CMOS logic. The DML model has unique feature that allows switching between both modes of operation as per the real-time system requirements. The DML functions in two dissimilar modes (static and dynamic) of operation with its specific features, to selectively obtain either low-energy or high-performance. The sub-threshold region DML achieves minimum-energy. However, sub-threshold region consequence in performance is enormous. In this paper, the working of DML model in the moderate inversion region has been explored. The near-threshold region holds much of the energy saving of subthreshold designs, along with improved performance. Furthermore, robustness to supply voltage and sensitivity to the process temperature variations are presented. Monte carol analysis shows that the projected near-threshold region has minimum energy along with the moderate performance.
Źródło:
International Journal of Electronics and Telecommunications; 2019, 65, 4; 723-729
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Whether the opinion about superiority of fuzzy controllers is justified
Autorzy:
Gessing, R.
Powiązania:
https://bibliotekanauki.pl/articles/199925.pdf
Data publikacji:
2010
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
fuzzy logic
fuzzy regulators
conventional regulators
Opis:
In the paper, using some MATLAB fuzzy logic toolbox Demos, in which the fuzzy controllers are compared with the classical PID ones, it is shown that the well tuned classical PID controllers are significantly better than those fuzzy presented in the Demos. It is shown, that using fuzzy approach, it is very difficult to shape the input-output nonlinearity, describing the so called fuzzy block of the fuzzy controller. It is also shown, that the linear fuzzy block (created to obtain comparable results with the classical PID controllers) is not justified at all, because it may be replaced by the usual summing junction, which is significantly simpler. The considerations of the paper do not support the idea of fuzzy controllers.
Źródło:
Bulletin of the Polish Academy of Sciences. Technical Sciences; 2010, 58, 1; 59-65
0239-7528
Pojawia się w:
Bulletin of the Polish Academy of Sciences. Technical Sciences
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Synthesis of Macro Petri Nets into FPGA with Distributed Memories
Autorzy:
Bukowiec, A.
Adamski, M.
Powiązania:
https://bibliotekanauki.pl/articles/226342.pdf
Data publikacji:
2012
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
decomposition
FGPAs
logic synthesis
Petri nets
Opis:
In this paper a new method of Petri net array-based synthesis is proposed. The method is based on decomposition of colored interpreted macro Petri net into state machine subnets. Each state machine subnet is determined by one color. During the decomposition process macroplaces are expanded or replaced by doublers of macroplace. Such decomposition leads to parallel implementation of a digital system. The structured encoding of places is done by using minimal numbers of bits. Colored microoperations, which are assigned to places, are written into distributed and flexible memories. It leads to realization of a logic circuit in a two-level concurrent structure, where the combinational circuit of the first level is responsible for firing transitions, and the second level memories are used for generation of microoperations. Such an approach allows balanced usage of different kinds of resources available in modern FPGAs.
Źródło:
International Journal of Electronics and Telecommunications; 2012, 58, 4; 403-410
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Center of circles intersection, a new defuzzification method for fuzzy numbers
Autorzy:
Zarzycki, H.
Dobrosielski, W. T.
Apiecionek, Ł.
Vince, T.
Powiązania:
https://bibliotekanauki.pl/articles/200363.pdf
Data publikacji:
2020
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
defuzzification
fuzzy logic
ordered fuzzy numbers
Opis:
The article introduces a new proposal of a def uzzification method, which can be implemented in fuzzy controllers. The first chapter refers to the origin of fuzzy sets. Next, a modern development based on this theory is presented in the form of ordered fuzzy numbers (OFN). The most important characteristics of ordered fuzzy numbers are also presented. In the following chapter, details about the defuzzification process are given as part of the fuzzy controller model. Then a new method of defuzzification is presented. The method is named center of circles intersection (CCI). The authors compare this method with a similar geometric solution: triangular expanding (TE) and geometric mean (GM). Also, the results are compared with other methods such as center of gravity (COG), first of maxima (FOM) and last of maxima (LOM). The analysis shows that the proposed solution works correctly and provides results for traditional fuzzy numbers as well as directed fuzzy numbers. The last chapter contains a summary, in which more detailed conclusions are provided and further directions of research are indicated.
Źródło:
Bulletin of the Polish Academy of Sciences. Technical Sciences; 2020, 68, 2; 185-190
0239-7528
Pojawia się w:
Bulletin of the Polish Academy of Sciences. Technical Sciences
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Technology mapping oriented to adaptive logic modules
Autorzy:
Kubica, M.
Kania, D.
Powiązania:
https://bibliotekanauki.pl/articles/200466.pdf
Data publikacji:
2019
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
decomposition
logic synthesis
technology mapping
ALM
Opis:
This paper presents an innovative method of technology mapping of the circuits in ALM appearing in FPGA devices by Intel. The essence of the idea is based on using triangle tables that are connected with different configurations of blocks. The innovation of the proposed method focuses on the possibility of choosing an appropriate configuration of an ALM block, which is connected with choosing an appropriate decomposition path. The effectiveness of the proposed technique of technology mapping is proved by experiments conducted on combinational and sequential circuits.
Źródło:
Bulletin of the Polish Academy of Sciences. Technical Sciences; 2019, 67, 5; 947-956
0239-7528
Pojawia się w:
Bulletin of the Polish Academy of Sciences. Technical Sciences
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Design Protection Using Logic Encryption and Scan-Chain Obfuscation Techniques
Autorzy:
Deepak, V. A.
Priyatharishini, M.
Devi, M. Nirmala
Powiązania:
https://bibliotekanauki.pl/articles/963795.pdf
Data publikacji:
2019
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
hardware security
obfuscation
logic encryption
scan-chain
Opis:
Due to increase in threats posed by offshore foundries, the companies outsourcing IPs are forced to protect their designs from the threats posed by the foundries. Few of the threats are IP piracy, counterfeiting and reverse engineering. To overcome these, logic encryption has been observed to be a leading countermeasure against the threats faced. It introduces extra gates in the design, known as key gates which hide the functionality of the design unless correct keys are fed to them. The scan tests are used by various designs to observe the fault coverage. These scan chains can become vulnerable to side-channel attacks. The potential solution for protection of this vulnerability is obfuscation of the scan output of the scan chain. This involves shuffling the working of the cells in the scan chain when incorrect test key is fed. In this paper, we propose a method to overcome the threats posed to scan design as well as the logic circuit. The efficiency of the secured design is verified on ISCAS’89 circuits and the results prove the security of the proposed method against the threats posed.
Źródło:
International Journal of Electronics and Telecommunications; 2019, 65, 3; 389-396
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Implementation of Algorithm of Petri Nets Distributed Synthesis into FPGA
Autorzy:
Bukowiec, A.
Tkacz, J.
Gratkowski, T.
Gidlewicz, T.
Powiązania:
https://bibliotekanauki.pl/articles/226156.pdf
Data publikacji:
2013
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
C#
decomposition
FGPA
logic synthesis
Petri net
Opis:
In the paper an implementation of algorithm of Petri net array-based synthesis is presented. The method is based on decomposition of colored interpreted macro Petri net into subnets. The structured encoding of places in subnets is done of using minimal numbers of bits. Microoperations, which are assigned to places, are written into distributed and flexible memories. It leads to realization of a logic circuit in a twolevel concurrent structure, where the combinational circuit of the first level is responsible for firing transitions, and the second level memories are used for generation of microoperations. This algorithm is implemented in C# and delivered as a stand alone library.
Źródło:
International Journal of Electronics and Telecommunications; 2013, 59, 4; 317-324
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Sprzeczność … i co dalej?
Contradiction … and what then?
Autorzy:
Hertrich-Woleński, Jan
Powiązania:
https://bibliotekanauki.pl/articles/577322.pdf
Data publikacji:
2015
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
logika
teoria
model
zastosowania
logic
theory
applications
Opis:
Artykuł dyskutuje możliwe postępowanie w sytuacji, gdy jakaś teoria okazuje się sprzeczna, a więc, gdy naruszona jest zasada sprzeczności, będąca jednym z tzw. najwyższych praw myślenia i równocześnie standardem racjonalności. W przypadku teorii matematycznych sprzeczność dyskwalifi kuje daną teorię i powoduje konieczność jej odrzucenia lub zmiany. Sytuacja w teoria empirycznych jest bardziej skomplikowana. Historia nauki dokumentuje, że teorie sprzeczne skutecznie pełniły swoją rolę. Jest tak dlatego, że sprzeczność może być izolowana i niejako pomijana. Niemniej jednak, tendencja do poprawy sprzecznej teorii jest naturalna także w przypadku teorii empirycznych.
The paper discusses a possible procedure in the case if a given theory appears to be inconsistent. It is just the case in which the principle of contradiction, as one of the so-called the highest rules of thinking and simultaneously a standard of rationality, is not obeyed. In the case of mathematical theories, contradictions disqualify a given theory and result in the necessity of their rejection or change. The problem of inconsistency of empirical theories is more complicated. The history of science provides an evidence that contradictory theories effectively play their role. It is because contradictions can be isolated and ignored to some extent. On the other hand, the tendency to improve an inconsistent theory is natural also in the case of empirical theories.
Źródło:
Zagadnienia Naukoznawstwa; 2015, 51, 3(205); 217-228
0044-1619
Pojawia się w:
Zagadnienia Naukoznawstwa
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Conception of Magnetic Memory Switched by Time Dependant Current Density and Current Electron Spin Polarization
Autorzy:
Steblinski, Paul
Blachowicz, Tomasz
Powiązania:
https://bibliotekanauki.pl/articles/227198.pdf
Data publikacji:
2019
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
spintronics
magnetic logic
BPM memories
magnetic simulations
Opis:
In this article the magnetic memory model with nano-meter size made from iron cells was proposed. For a purpose of determining the model specifications, the magnetic probes group with different geometrical parameters were examined using numeric simulations for the two different time duration of transitions among quasi-stable magnetic distributions found in the system, derived from the energy minimums. The geometrical parameters range was found, for which the 16 quasi–stable energetic states exist for the each probe. Having considered these results the 4 bits magnetic cells systems can be designed whose state is changed by spin-polarized current. Time dependent current densities and the current electron spin polarization directions were determined for all cases of transitions among quasi-stable states, for discovered set of 4 bits cells with different geometrical parameters. The 16-states cells, with the least geometrical area, achieved the 300 times bigger writing density in comparison to actual semiconductor solutions with the largest writing densities. The transitions among quasi-stable states of cells were examined for the time durations 10⁵ times shorter than that for up to date solutions.
Źródło:
International Journal of Electronics and Telecommunications; 2019, 65, 2; 309-312
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Wyświetlanie 1-15 z 101

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