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Wyszukujesz frazę "interconnections" wg kryterium: Temat


Wyświetlanie 1-2 z 2
Tytuł:
A Method to Support Diagnostics of Dynamic Faults in Networks of Interconnections
Autorzy:
Garbolino, T.
Powiązania:
https://bibliotekanauki.pl/articles/226237.pdf
Data publikacji:
2018
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
network of interconnections
system-on-chip
diagnostics
MISR
compaction
signature
Chinese remainder theorem
Opis:
The article is devoted to the method facilitating the diagnostics of dynamic faults in networks of interconnection in systems-on-chips. It shows how to reconstruct the erroneous test response sequence coming from the faulty connection based on the set of signatures obtained as a result of multiple compaction of this sequence in the MISR register with programmable feedback. The Chinese reminder theorem is used for this purpose. The article analyzes in detail the various hardware realizations of the discussed method. The testing time associated with each proposed solution was also estimated. Presented method can be used with any type of test sequence and test pattern generator. It is also easily scalable to any number of nets in the network of interconnections. Moreover, it supports finding a trade-off between area overhead and testing time.
Źródło:
International Journal of Electronics and Telecommunications; 2018, 64, 3; 407-420
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
New Structure of Test Pattern Generator Stimulating Crosstalks in Bus-type Connections
Autorzy:
Garbolino, T.
Powiązania:
https://bibliotekanauki.pl/articles/226543.pdf
Data publikacji:
2015
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
integrated circuit interconnections
crosstalk
test pattern generator
built-in self-test
system-on-a-chip
Opis:
The paper discloses the idea of a new structure for a Test Pattern Generator (TPG) for detection of crosstalk faults that may happen to bus-type interconnections between built in blocks within a System-on-Chip structure. The new idea is an improvement of the TPG design proposed by the author in one of the previous studies. The TPG circuit is meant to generate test sequences that guarantee detection of all crosstalk faults with the capacitive nature that may occur between individual lines within an interconnecting bus. The study comprises a synthesizable and parameterized model developed for the presented TPG in the VLSI Hardware Description Language (VHDL) with further investigation of properties and features of the offered module. The significant advantages of the proposed TPG structure include less area occupied on a chip and higher operation frequency as compared to other solutions. In addition, the design demonstrates good scalability in terms of both the hardware overhead and the length of the generated test sequence.
Źródło:
International Journal of Electronics and Telecommunications; 2015, 61, 1; 67-75
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
    Wyświetlanie 1-2 z 2

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