Temat: floating point - Katalog OPAC zbiorów

Skocz do pozycji: 1.

Tytuł:: Fuzzy Processing Implementation in Dedicated Digital Hardware
Autorzy:: Szecówka, P. M.
Musiał, A.
Powiązania:: https://bibliotekanauki.pl/articles/226691.pdf
Data publikacji:: 2010
Wydawca:: Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:: fuzzy
hardware
floating point
VHDL
FPGA
Opis:: The paper presents a concept of digital circuit dedicated for fuzzy processing with numerical inputs and outputs. Partially concurrent and pipelined data flow provides high performance, with relatively low dependence on particular algorithm complexity. Sample design with triangular fuzzy sets, rule strength calculation (minimum approach) and defuzzyfication by weighted sum of fuzzy sets centers was implemented in VHDL, verified and synthesized for FPGA. Floating point arithmetic was applied, including dvision performed by dedicated synchronous machine. All modules were prepared for easy reuse/redesign.
Źródło:: International Journal of Electronics and Telecommunications; 2010, 56, 4; 405-410
2300-1933
Pojawia się w:: International Journal of Electronics and Telecommunications
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 2.

Tytuł:: A MUX based signed-floating-point MAC architecture using UCM algorithm
Autorzy:: Sarma, R.
Bhargava, C.
Jain, S.
Powiązania:: https://bibliotekanauki.pl/articles/201240.pdf
Data publikacji:: 2020
Wydawca:: Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:: floating-point MAC
UCM
cadence
TSMC 130 nm
GPDK 90 nm
Opis:: Digital system algorithms such as FFT algorithms, convolution, image processing algorithm, etc. deploy Multiply and Accumulate (MAC) unit as an evaluative component. The efficiency of a MAC typically relies on the speed of operation, power dissipation, and chip area along with the complexity level of the circuit. In this research paper, a power-delay-efficient signed-floating-point MAC (SFMAC) is proposed using Universal Compressor based Multiplier (UCM). Instead of having a complex design architecture, a simple multiplexer-based circuit is used to achieve a signed-floating output. The 8x8 SFMAC can take 8-bit mantissa and 3-bit exponent and therefore, the input to the SFMAC can be in the range of – (7.96875)10 to +(7.96875)10. The design and implementation of the proposed architecture is executed on the Cadence Spectre tool in GPDK 90 nm and TSMC 130 nm CMOS, which proves as power and delay efficient.
Źródło:: Bulletin of the Polish Academy of Sciences. Technical Sciences; 2020, 68, 4; 835-844
0239-7528
Pojawia się w:: Bulletin of the Polish Academy of Sciences. Technical Sciences
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 3.

Tytuł:: Novel architecture for floating point accumulator with cancelation error detection
Autorzy:: Jamro, E.
Dąbrowska-Boruch, A.
Russek, P.
Wielgosz, M.
Wiatr, K.
Powiązania:: https://bibliotekanauki.pl/articles/201228.pdf
Data publikacji:: 2018
Wydawca:: Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:: floating point arithmetic
computing error
approximate computing
arytmetyka zmiennoprzecinkowa
błąd obliczeniowy
obliczenia przybliżone
Opis:: A floating point accumulator cannot be obtained straightforwardly due to its pipeline architecture and feedback loop. Therefore, an essential part of the proposed floating point accumulator is a critical accumulation loop which is limited to an integer adder and 16-bit shifter only. The proposed accumulator detects a catastrophic cancellation which occurs e.g. when two similar numbers are subtracted. Additionally, modules with reduced hardware resources for rough error evaluation are proposed. The proposed architecture does not comply with the IEEE-754 floating point standard but it guarantees that a correct result, with an arbitrarily defined number of significant bits, is obtained. The proposed calculation philosophy focuses on the desired result error rather than on calculation precision as such.
Źródło:: Bulletin of the Polish Academy of Sciences. Technical Sciences; 2018, 66, 5; 579-587
0239-7528
Pojawia się w:: Bulletin of the Polish Academy of Sciences. Technical Sciences
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 4.

Tytuł:: Hardware implementation of hyperbolic tangent and sigmoid activation functions
Autorzy:: Hajduk, Z.
Powiązania:: https://bibliotekanauki.pl/articles/200063.pdf
Data publikacji:: 2018
Wydawca:: Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:: FPGA
hyperbolic tangent
sigmoid
floating point arithmetic
tangens hiperboliczny
arytmetyka zmiennoprzecinkowa
funkcja sigmoidalna
Opis:: This paper presents the high accuracy hardware implementation of the hyperbolic tangent and sigmoid activation functions for artificial neural networks. A kind of a direct implementation of the functions in a few different versions is proposed and investigated both by software and hardware modeling. A single precision floating point arithmetic is applied. Apart from conventional design style with hardware description language coding, high level synthesis design techniques with the Matlab HDL coder and Xilinx Vivado HLS have also been investigated.
Źródło:: Bulletin of the Polish Academy of Sciences. Technical Sciences; 2018, 66, 5; 563-577
0239-7528
Pojawia się w:: Bulletin of the Polish Academy of Sciences. Technical Sciences
Dostawca treści:: Biblioteka Nauki

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