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Wyświetlanie 1-3 z 3
Tytuł:
Analysis of High-Performance Near-threshold Dual Mode Logic Design
Autorzy:
Bikki, Pavankumar
Powiązania:
https://bibliotekanauki.pl/articles/226748.pdf
Data publikacji:
2019
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
CMOS logic
dual mode logic
dynamic mode
high performance
minimum energy point
near-threshold
Opis:
A novel dual mode logic (DML) model has a superior energy-performance compare to CMOS logic. The DML model has unique feature that allows switching between both modes of operation as per the real-time system requirements. The DML functions in two dissimilar modes (static and dynamic) of operation with its specific features, to selectively obtain either low-energy or high-performance. The sub-threshold region DML achieves minimum-energy. However, sub-threshold region consequence in performance is enormous. In this paper, the working of DML model in the moderate inversion region has been explored. The near-threshold region holds much of the energy saving of subthreshold designs, along with improved performance. Furthermore, robustness to supply voltage and sensitivity to the process temperature variations are presented. Monte carol analysis shows that the projected near-threshold region has minimum energy along with the moderate performance.
Źródło:
International Journal of Electronics and Telecommunications; 2019, 65, 4; 723-729
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Backstepping sliding mode controller improved with fuzzy logic: Application to the quadrotor helicopter
Autorzy:
Zeghlache, S.
Saigaa, D.
Harrag, A.
Kara, K.
Bouguerra, A.
Powiązania:
https://bibliotekanauki.pl/articles/229480.pdf
Data publikacji:
2012
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
fuzzy sliding mode
backstepping
quadrotor helicopter
dynamic modeling
Opis:
n this paper we present a new design method for the fight control of an autonomous quadrotor helicopter based on fuzzy sliding mode control using backstepping approach. Due to the underactuated property of the quadrotor helicopter, the controller can move three positions (x;y; z) of the helicopter and the yaw angle to their desired values and stabilize the pitch and roll angles. A first-order nonlinear sliding surface is obtained using the backstepping technique, on which the developed sliding mode controller is based. Mathematical development for the stability and convergence of the system is presented. The main purpose is to eliminate the chattering phenomenon. Thus we have used a fuzzy logic control to generate the hitting control signal. The performances of the nonlinear control method are evaluated by simulation and the results demonstrate the effectiveness of the proposed control strategy for the quadrotor helicopter in vertical flights.
Źródło:
Archives of Control Sciences; 2012, 22, 3; 315-342
1230-2384
Pojawia się w:
Archives of Control Sciences
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
A 1.67 pJ/Conversion-step 8-bit SAR-Flash ADC Architecture in 90-nm CMOS Technology
Autorzy:
Khatak, Anil
Kumar, Manoj
Dhull, Sanjeev
Powiązania:
https://bibliotekanauki.pl/articles/1844527.pdf
Data publikacji:
2021
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
analog to digital converter
ADC
successive approximation register (SAR)
common mode current feedback gain boosting
CMFD-GB
residue amplifier
RA
spurious free dynamic range
SFDR
integral nonlinearity
INL
differential nonlinearity
DNL
Opis:
A novice advanced architecture of 8-bit analog to digital converter is introduced and analyzed in this paper. The structure of proposed ADC is based on the sub-ranging ADC architecture in which a 4-bit resolution flash-ADC is utilized. The proposed ADC architecture is designed by employing a comparator which is equipped with common mode current feedback and gain boosting technique (CMFD-GB) and a residue amplifier. The proposed 8 bits ADC structure can achieve the speed of 140 mega-samples per second. The proposed ADC architecture is designed at a resolution of 8 bits at 10 MHz sampling frequency. DNL and INL values of the proposed design are -0.94/1.22 and -1.19/1.19 respectively. The ADC design dissipates a power of 1.24 mW with the conversion speed of 0.98 ns. The magnitude of SFDR and SNR from the simulations at Nyquist input is 39.77 and 35.62 decibel respectively. Simulations are performed on a SPICE based tool in 90 nm CMOS technology. The comparison shows better performance for this proposed ADC design in comparison to other ADC architectures regarding speed, resolution and power consumption.
Źródło:
International Journal of Electronics and Telecommunications; 2021, 67, 3; 347-354
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
    Wyświetlanie 1-3 z 3

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