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    Wyświetlanie 1-9 z 9
    Tytuł:
    DAC testing using modulated signals
    Autorzy:
    Fexa, P.
    Verdal, J.
    Svatoš, J.
    Powiązania:
    https://bibliotekanauki.pl/articles/220431.pdf
    Data publikacji:
    2011
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    digital-to-analog converter
    ENOB
    Signal-to-noise and distortion - SINAD
    FFT analysis
    Crest Factor (CF)
    Opis:
    This document analyses qualities of methods used for testing dynamical parameters of Digital-to-Analog Converters (DAC) using a multi-frequency signal. As the source for these signals, Amplitude Modulated (AM) and Frequency Modulated (FM) signals are used. These signals are often used in radio engineering. Results of the tests, like Effective Number of Bits (ENOB), Signal-to-Noise and Distortion (SINAD), are evaluated in the frequency domain and they are compared with standard results of Sine Wave FFT test methods. The aim of this research is firstly to test whether it is possible to test a DAC using modulated signals, secondly to reduce testing time, while estimating band performance of DAC.
    Źródło:
    Metrology and Measurement Systems; 2011, 18, 2; 283-293
    0860-8229
    Pojawia się w:
    Metrology and Measurement Systems
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Logarithmic ADC with Accumulation of Charge and Impulse Feedback : Construction, Principle of Operation and Dynamic Properties
    Autorzy:
    Mychuda, Zynoviy
    Mychuda, Lesya
    Antoniv, Uliana
    Szcześniak, Adam
    Powiązania:
    https://bibliotekanauki.pl/articles/2055218.pdf
    Data publikacji:
    2021
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    analog-to-digital converter
    analysis
    construction
    charge accumulation
    logarithm
    modeling
    impulse feedback
    Opis:
    This article is a presentation of the analysis of new class of logarithmic analog-to-digital converter (LADC) with accumulation of charge and impulse feedback. LADC construction, principle of operation and dynamic properties were presented. They can also be part of more complex converters and systems based on LADC. LADC of this class is perspective for implementation in the form of integrated circuit, as the number of switched capacitors needed to conversion is minimized to one capacitor. (Logarithmic ADC with accumulation of charge and impulse feedback – construction, principle of operation and dynamic properties).
    Źródło:
    International Journal of Electronics and Telecommunications; 2021, 67, 4; 699--704
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Logarithmic ADC with Accumulation of Charge and Impulse Feedback : Analysis and Modeling
    Autorzy:
    Mychuda, Zynoviy
    Mychuda, Lesya
    Antoniv, Uliana
    Szcześniak, Adam
    Powiązania:
    https://bibliotekanauki.pl/articles/2055223.pdf
    Data publikacji:
    2021
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    analog-to-digital converter
    analysis
    construction
    charge accumulation
    logarithm
    modeling
    impulse feedback
    Opis:
    This article is a presentation of the analysis of new class of logarithmic analog-to-digital converter (LADC) with accumulation of charge and impulse feedback. Development of mathematical models of errors, quantitative assessment of these errors taking into account modern components and assessing the accuracy of logarithmic analog-to-digital converter (LADC) with accumulation of charge and impulse feedback were presented. (Logarithmic ADC with accumulation of charge and impulse feedback – analysis and modeling).
    Źródło:
    International Journal of Electronics and Telecommunications; 2021, 67, 4; 705--710
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Estimation and correction of gain mismatch and timing error in time-interleaved ADCs based on DFT
    Autorzy:
    Guo, L.
    Tian, S.
    Wang, Z.
    Powiązania:
    https://bibliotekanauki.pl/articles/221135.pdf
    Data publikacji:
    2014
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    correction
    estimation
    gain mismatch
    time-interleaved analog-to-digital converter
    timing error
    Opis:
    Time-interleaved analog-to-digital converter (ADC) architecture is crucial to increase the maximum sample rate. However, offset mismatch, gain mismatch, and timing error between time-interleaved channels degrade the performance of time-interleaved ADCs. This paper focuses on the gain mismatch and timing error. Techniques based on Discrete Fourier Transform (DFT) for estimating and correcting gain mismatch and timing error in an M-channel ADC are depicted. Numerical simulations are used to verify the proposed estimation and correction algorithm.
    Źródło:
    Metrology and Measurement Systems; 2014, 21, 3; 535-544
    0860-8229
    Pojawia się w:
    Metrology and Measurement Systems
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    On the bias of terminal based gain and offset estimation using the ADC histogram test method
    Autorzy:
    Correa Alegria, F.
    Tiglao, N. M. C.
    Powiązania:
    https://bibliotekanauki.pl/articles/221033.pdf
    Data publikacji:
    2011
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    analog to digital converter
    histogram test method
    estimator bias
    terminal based
    gain
    offset
    Opis:
    The Histogram Test method is a popular technique in analog-to-digital converter (ADC) testing. The presence of additive noise in the test setup or in the ADC itself can potentially affect the accuracy of the test results. In this study, we demonstrate that additive noise causes a bias in the terminal based estimation of the gain but not in the estimation of the offset. The estimation error is determined analytically as a function of the sinusoidal stimulus signal amplitude and the noise standard deviation. We derive an exact but computationally difficult expression as well as a simpler closed form approximation that provides an upper bound of the bias of the terminal based gain. The estimators are validated numerically using a Monte Carlo procedure with simulated and experimental data.
    Źródło:
    Metrology and Measurement Systems; 2011, 18, 1; 3-12
    0860-8229
    Pojawia się w:
    Metrology and Measurement Systems
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    A Novel Design Of An NTC Thermistor Linearization Circuit
    Autorzy:
    Lukić, J.
    Denić, D.
    Powiązania:
    https://bibliotekanauki.pl/articles/221560.pdf
    Data publikacji:
    2015
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    linearization
    NTC thermistor
    piecewise linear flash analog-to-digital converter
    serial-parallel resistive voltage divider
    Opis:
    A novel design of a circuit used for NTC thermistor linearization is proposed. The novelty of the proposed design consists in a specific combination of two linearization circuits, a serial-parallel resistive voltage divider and a two-stage piecewise linear analog-to-digital converter. At the output of the first linearization circuit the quasi-linear voltage is obtained. To remove the residual voltage nonlinearity, the second linearization circuit, i.e., a two-stage piecewise linear analog-to-digital converter is employed. This circuit is composed of two flash analog-to-digital converters. The first analog-to-digital converter is piecewise linear and it is actually performing the linearization, while the second analog-to-digital converter is linear and it is performing the reduction of the quantization error introduced by the first converter. After the linearization is performed, the maximal absolute value of a difference between the measured and real temperatures is 0.014°C for the temperature range between - 25 and 75°C, and 0.001°C for the temperature range between 10 and 40°C.
    Źródło:
    Metrology and Measurement Systems; 2015, 22, 3; 351-362
    0860-8229
    Pojawia się w:
    Metrology and Measurement Systems
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Disassembly-free metrological control of analog-to-digital converter parameters
    Autorzy:
    Bubela, Tetiana
    Kochan, Roman
    Więcław, Łukasz
    Yatsuk, Vasyl
    Kuts, Victor
    Yatsuk, Jurij
    Powiązania:
    https://bibliotekanauki.pl/articles/2173896.pdf
    Data publikacji:
    2022
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    metrological support
    analog-to-digital converter
    non-disassembly control
    cyber-physical system
    nonlinearity
    additive component of error
    ACE
    multiplicative component of error
    Opis:
    The authors update the issue disassembly-free control and correction of all components of the error of measuring channels with multi-bit analog-to-digital converters (ADCs). The main disadvantages of existing methods for automatic control of the parameters of multi-bit ADCs, in particular their nonlinearity, are identified. Methods for minimizing instrumental errors and errors caused by limited internal resistances of closed switches, input and output resistances of active elements are investigated. The structures of devices for determining the multiplicative and nonlinear components of the error of multi-bit ADCs based on resistive dividers built on single-nominal resistors are proposed and analyzed. The authors propose a method for the correction of additive, multiplicative and nonlinear components of the error at each of the specified points of the conversion range during non-disassembly control of the ADC with both types of inputs. The possibility of non-disassembly control, as well as correction of multiplicative and nonlinear components of the error of multi-bit ADCs in the entire range of conversion during their on-site control is proven. ADC error correction procedures are proposed. These procedures are practically invariant to the non-informative parameters of active structures with resistive dividers composed of single-nominal resistors. In the article the prospects of practical implementation of the method of error correction during non-dismantling control of ADC parameters using the possibilities provided by modern microelectronic components are shown. The ways to minimize errors are proposed and the requirements to the choice of element parameters for the implementation of the proposed technical solutions are given. It is proved that the proposed structure can be used for non-disassembly control of multiplicative and nonlinear components of the error of precision instrumentation amplifiers.
    Źródło:
    Metrology and Measurement Systems; 2022, 29, 4; 669--684
    0860-8229
    Pojawia się w:
    Metrology and Measurement Systems
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    A 1.67 pJ/Conversion-step 8-bit SAR-Flash ADC Architecture in 90-nm CMOS Technology
    Autorzy:
    Khatak, Anil
    Kumar, Manoj
    Dhull, Sanjeev
    Powiązania:
    https://bibliotekanauki.pl/articles/1844527.pdf
    Data publikacji:
    2021
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    analog to digital converter
    ADC
    successive approximation register (SAR)
    common mode current feedback gain boosting
    CMFD-GB
    residue amplifier
    RA
    spurious free dynamic range
    SFDR
    integral nonlinearity
    INL
    differential nonlinearity
    DNL
    Opis:
    A novice advanced architecture of 8-bit analog to digital converter is introduced and analyzed in this paper. The structure of proposed ADC is based on the sub-ranging ADC architecture in which a 4-bit resolution flash-ADC is utilized. The proposed ADC architecture is designed by employing a comparator which is equipped with common mode current feedback and gain boosting technique (CMFD-GB) and a residue amplifier. The proposed 8 bits ADC structure can achieve the speed of 140 mega-samples per second. The proposed ADC architecture is designed at a resolution of 8 bits at 10 MHz sampling frequency. DNL and INL values of the proposed design are -0.94/1.22 and -1.19/1.19 respectively. The ADC design dissipates a power of 1.24 mW with the conversion speed of 0.98 ns. The magnitude of SFDR and SNR from the simulations at Nyquist input is 39.77 and 35.62 decibel respectively. Simulations are performed on a SPICE based tool in 90 nm CMOS technology. The comparison shows better performance for this proposed ADC design in comparison to other ADC architectures regarding speed, resolution and power consumption.
    Źródło:
    International Journal of Electronics and Telecommunications; 2021, 67, 3; 347-354
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Sampling Jitter in Audio A/D Converters
    Autorzy:
    Kulka, Z.
    Powiązania:
    https://bibliotekanauki.pl/articles/177046.pdf
    Data publikacji:
    2011
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    analog-to-digital converter
    ADC
    successive approximation register (SAR)
    sigma-delta ADC
    sample-and-hold circuit
    DT sigma delta modulator
    CT sigma delta modulator
    time jitter
    aperture jitter
    clock jitter
    periodic clock jitter
    signal-to-noise ratio (SNR)
    Opis:
    This paper provides an overview of the effects of timing jitter in audio sampling analog-to-digital converters (ADCs), i.e. PCM (conventional or Nyquist sampling) ADCs and sigma-delta (ΣΔ) ADCs. Jitter in a digital audio is often defined as short- term fluctuations of the sampling instants of a digital signal from their ideal positions in time. The influence of the jitter increases particularly with the improvements in both resolution and sampling rate of today’s audio ADCs. At higher frequencies of the input signals the sampling jitter becomes a dominant factor in limiting the ADCs performance in terms of signal-to-noise ratio (SNR) and dynamic range (DR).
    Źródło:
    Archives of Acoustics; 2011, 36, 4; 831-849
    0137-5075
    Pojawia się w:
    Archives of Acoustics
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-9 z 9

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