- Tytuł:
- A 1.67 pJ/Conversion-step 8-bit SAR-Flash ADC Architecture in 90-nm CMOS Technology
- Autorzy:
-
Khatak, Anil
Kumar, Manoj
Dhull, Sanjeev - Powiązania:
- https://bibliotekanauki.pl/articles/1844527.pdf
- Data publikacji:
- 2021
- Wydawca:
- Polska Akademia Nauk. Czytelnia Czasopism PAN
- Tematy:
-
analog to digital converter
ADC
successive approximation register (SAR)
common mode current feedback gain boosting
CMFD-GB
residue amplifier
RA
spurious free dynamic range
SFDR
integral nonlinearity
INL
differential nonlinearity
DNL - Opis:
- A novice advanced architecture of 8-bit analog to digital converter is introduced and analyzed in this paper. The structure of proposed ADC is based on the sub-ranging ADC architecture in which a 4-bit resolution flash-ADC is utilized. The proposed ADC architecture is designed by employing a comparator which is equipped with common mode current feedback and gain boosting technique (CMFD-GB) and a residue amplifier. The proposed 8 bits ADC structure can achieve the speed of 140 mega-samples per second. The proposed ADC architecture is designed at a resolution of 8 bits at 10 MHz sampling frequency. DNL and INL values of the proposed design are -0.94/1.22 and -1.19/1.19 respectively. The ADC design dissipates a power of 1.24 mW with the conversion speed of 0.98 ns. The magnitude of SFDR and SNR from the simulations at Nyquist input is 39.77 and 35.62 decibel respectively. Simulations are performed on a SPICE based tool in 90 nm CMOS technology. The comparison shows better performance for this proposed ADC design in comparison to other ADC architectures regarding speed, resolution and power consumption.
- Źródło:
-
International Journal of Electronics and Telecommunications; 2021, 67, 3; 347-354
2300-1933 - Pojawia się w:
- International Journal of Electronics and Telecommunications
- Dostawca treści:
- Biblioteka Nauki
Artykuł