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    Tytuł:
    Performance of Non-Binary LDPC Codes for Next Generation Mobile Systems
    Autorzy:
    Gierszal, H.
    Hołubowicz, W.
    Kiedrowski, Ł.
    Flizikowski, A.
    Powiązania:
    https://bibliotekanauki.pl/articles/226906.pdf
    Data publikacji:
    2010
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    LDPC
    mobile systems
    modulation schemes
    non-binary
    Opis:
    A new family of non-binary LDPC is presented that are based on a finite field GF(64). They may be successfully implemented in single-carrier and OFDM transmission system. Results prove that DAVINCI codes allow for improving the system performance and may be considered to be applied in the future mobile system.
    Źródło:
    International Journal of Electronics and Telecommunications; 2010, 56, 2; 111-116
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    WiMAX Cell Level Simulation Platform Based on ns-2 and DSP Integration
    Autorzy:
    Flizikowski, A.
    Kozik, R.
    Gierszal, H.
    Przybyszewski, M.
    Hołubowicz, W.
    Powiązania:
    https://bibliotekanauki.pl/articles/226960.pdf
    Data publikacji:
    2010
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    FEC codes
    nb-LDPC
    DSP
    integrated platform
    ns-2
    Opis:
    The WiMAX (Worldwide Interoperability for Microwave Access) system based on the IEEE 802.16 family of standards is a promising technology for last-mile access. Both IEEE 802.16 and 3GPP-LTE systems candidate for becoming the 4G network of choice. The need to evaluate multiple performance enhancing techniques like MIMO, OFDM(A), novel channel coding schemes like non-binary LDPC codes, together with development of standards like IEEE 802.21, that aims at enabling handover and interoperability between heterogeneous network types, make rapid prototyping-based simulations an important issue. This paper presents a novel approach to 4G-oriented simulation environment that integrates popular network simulator (ns-2) and a Digital Signal Processing (DSP) to enable comprehensive link layer and cell level simulations. Proposed simulation environment is intended as an evaluation platform for assessing QoS/QoE and Connection Admission Control (CAC) algorithms designed for WiMAX systems. Moreover we study ways to improve simulation time (with focus on AWGN channel simulation) by using CUDA parallel processing technology for NVIDIA graphic cards.
    Źródło:
    International Journal of Electronics and Telecommunications; 2010, 56, 2; 169-176
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Pipeline processing in low-density parity-check codes hardware decoder
    Autorzy:
    Sułek, W.
    Powiązania:
    https://bibliotekanauki.pl/articles/202316.pdf
    Data publikacji:
    2011
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    channel coding
    LDPC codes
    iterative decoding
    decoder implementation
    pipelined processing
    Opis:
    Low-Density Parity-Check (LDPC) codes are one of the best known error correcting coding methods. This article concerns the hardware iterative decoder for a subclass of LDPC codes that are implementation oriented, known also as Architecture Aware LDPC. The decoder has been implemented in a form of synthesizable VHDL description. To achieve high clock frequency of the decoder hardware implementation – and in consequence high data-throughput, a large number of pipeline registers has been used in the processing chain. However, the registers increase the processing path delay, since the number of clock cycles required for data propagating is increased. Thus in general the idle cycles must be introduced between decoding subiterations. In this paper we study the conditions for necessity of idle cycles and provide a method for calculation the exact number of required idle cycles on the basis of parity check matrix of the code. Then we propose a parity check matrix optimization method to minimize the total number of required idle cycles and hence, maximize the decoder throughput. The proposed matrix optimization by sorting rows and columns does not change the code properties. Results, presented in the paper, show that the decoder throughput can be significantly increased with the proposed optimization method.
    Źródło:
    Bulletin of the Polish Academy of Sciences. Technical Sciences; 2011, 59, 2; 149-155
    0239-7528
    Pojawia się w:
    Bulletin of the Polish Academy of Sciences. Technical Sciences
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Optimizing the Bit-flipping Method for Decoding Low-density Parity-check Codes in Wireless Networks by Using the Artificial Spider Algorithm
    Autorzy:
    Ghaffoori, Ali Jasim
    Abdul-Adheem, Wameedh Riyadh
    Powiązania:
    https://bibliotekanauki.pl/articles/2055251.pdf
    Data publikacji:
    2022
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    low-density parity-check
    LDPC
    hard-decision Bit-Flipping
    BF
    particle swarm optimization
    PSO
    artificial spider algorithm
    ASA
    Opis:
    In this paper, the performance of Low-Density Parity-Check (LDPC) codes is improved, which leads to reduce the complexity of hard-decision Bit-Flipping (BF) decoding by utilizing the Artificial Spider Algorithm (ASA). The ASA is used to solve the optimization problem of decoding thresholds. Two decoding thresholds are used to flip multiple bits in each round of iteration to reduce the probability of errors and accelerate decoding convergence speed while improving decoding performance. These errors occur every time the bits are flipped. Then, the BF algorithm with a low-complexity optimizer only requires real number operations before iteration and logical operations in each iteration. The ASA is better than the optimized decoding scheme that uses the Particle Swarm Optimization (PSO) algorithm. The proposed scheme can improve the performance of wireless network applications with good proficiency and results. Simulation results show that the ASA-based algorithm for solving highly nonlinear unconstrained problems exhibits fast decoding convergence speed and excellent decoding performance. Thus, it is suitable for applications in broadband wireless networks.
    Źródło:
    International Journal of Electronics and Telecommunications; 2022, 68, 1; 109--114
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    The design of structured LDPC codes with algorithmic graph construction
    Autorzy:
    Sułek, Wojciech
    Powiązania:
    https://bibliotekanauki.pl/articles/2173691.pdf
    Data publikacji:
    2022
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    channel coding
    low density parity check code
    LDPC
    nonbinary code
    quasi-cyclic code
    kodowanie kanałowe
    kodowanie niebinarne
    kodowanie quasi-cykliczne
    kodowanie korekcyjne
    Opis:
    Low-Density Parity-Check (LDPC) codes are among the most effective modern error-correcting codes due to their excellent correction performance and highly parallel decoding scheme. Moreover, the nonbinary extension of such codes further increases performance in the short-block regime. In this paper, we review the key elements for the construction of implementation-oriented binary and nonbinary codes. These Quasi-Cyclic LDPC (QC-LDPC) codes additionally feature efficient encoder and decoder implementation frameworks. We then present a versatile algorithm for the construction of both binary and nonbinary QC-LDPC codes that have low encoding complexity and an optimized corresponding graph structure. Our algorithm uses a progressive edge growth algorithm, modified for QC-LDPC graph construction, and then performs an iterative global search for optimized cyclic shift values within the QC-LDPC circulants. Strong error correction performance is achieved by minimizing the number of short cycles, and cycles with low external connectivity, within the code graph. We validate this approach via error rate simulations of a transmission system model featuring an LDPC coder-decoder, digital modulation, and additive white Gaussian noise channels. The obtained numerical results validate the effectiveness of the proposed construction algorithm, with a number of constructed codes exhibiting either similar or superior performance to industry standard binary codes and selected nonbinary codes from the literature.
    Źródło:
    Bulletin of the Polish Academy of Sciences. Technical Sciences; 2022, 70, 4; art. no. e141592
    0239-7528
    Pojawia się w:
    Bulletin of the Polish Academy of Sciences. Technical Sciences
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-5 z 5

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