- Tytuł:
- Power equalization of AES FPGA implementation
- Autorzy:
-
Strachacki, M.
Szczepański, S. - Powiązania:
- https://bibliotekanauki.pl/articles/199907.pdf
- Data publikacji:
- 2010
- Wydawca:
- Polska Akademia Nauk. Czytelnia Czasopism PAN
- Tematy:
-
AES
FPGA
cryptography
side channel attack
DPA
power analysis
power equalization - Opis:
- This paper briefly introduces side channel attacks on cryptographic hardware with special emphasis on differential power analysis (DPA). Based on existing countermeasures against DPA, design method combining power equalization for synchronous and combinatorial circuits has been proposed. AES algorithm has been implemented in Xilinx Spartan II-E field programmable gate array (FPGA) device using the standard and power-equalized methods. Power traces for DPA have been collected using XPower tool. Simulation results show that standard AES implementation can be broken after N=500 encryptions, while power-equalized counterpart shows no correlation between power consumption and the cipher key after N=2000 encryptions.
- Źródło:
-
Bulletin of the Polish Academy of Sciences. Technical Sciences; 2010, 58, 1; 125-128
0239-7528 - Pojawia się w:
- Bulletin of the Polish Academy of Sciences. Technical Sciences
- Dostawca treści:
- Biblioteka Nauki
Artykuł