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    Wyświetlanie 1-4 z 4
    Tytuł:
    Low Power, High Dynamic Range Analogue Multiplexer for Multi-Channel Parallel Recording of Neuronal Signals Using Multi-Electrode Arrays
    Autorzy:
    Rydygier, P.
    Dąbrowski, W.
    Fiutowski, T.
    Wiącek, P.
    Powiązania:
    https://bibliotekanauki.pl/articles/226679.pdf
    Data publikacji:
    2010
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    analogue multiplexer
    low power amplifier
    multi-channel electronics
    multielectrode arrays
    neural signal
    Opis:
    In the paper we present the design and test resultsof an integrated circuit combining a sample & hold circuit andan analogue multiplexer. The circuit has been designed as abuilding block for a multi-channel Application Specific IntegratedCircuit (ASIC) for recording signals from alive neuronal tissueusing high-density micro-electrode arrays (MEAs). The designis optimised with respect to critical requirements for suchapplications, i.e. short sampling time, low power dissipation, goodl inearity and high dynamic range. Presented design comprisessample&hold circuits with class AB operational amplifier, novelshift register, which allows minimising cross-coupling of the clocksignal and control logic. The circuit has been designed in 0.35µm CMOS process and has been successfully implemented in aprototype multi-channel ASIC.
    Źródło:
    International Journal of Electronics and Telecommunications; 2010, 56, 4; 399-404
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Low-Power High-Speed Double Gate 1-bit Full Adder Cell
    Autorzy:
    Kumar, R.
    Roy, S.
    Bhunia, C. T.
    Powiązania:
    https://bibliotekanauki.pl/articles/226653.pdf
    Data publikacji:
    2016
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    low-power full-adder
    low-power CMOS design
    multiplexer based full-adder design
    multi-threshold voltage based full-adder design
    pass transmission logic
    Opis:
    In this paper, we proposed an efficient full adder circuit using 16 transistors. The proposed high-speed adder circuit is able to operate at very low voltage and maintain the proper output voltage swing and also balance the power consumption and speed. Proposed design is based on CMOS mixed threshold voltage logic (MTVL) and implemented in 180nm CMOS technology. In the proposed technique the most time-consuming and power consuming XOR gates and multiplexer are designed using MTVL scheme. The maximum average power consumed by the proposed circuit is 6.94μW at 1.8V supply voltage and frequency of 500 MHz, which is less than other conventional methods. Power, delay, and area are optimized by using pass transistor logic and verified using the SPICE simulation tool at desired broad frequency range. It is also observed that the proposed design may be successfully utilized in many cases, especially whenever the lowest power consumption and delay are aimed.
    Źródło:
    International Journal of Electronics and Telecommunications; 2016, 62, 4; 329-334
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Compact Transverse Electric Silicon-on-Insulator Mode Converter for Mode-Division Multiplexer
    Autorzy:
    Sharaf, Mohamed H.
    El-Mashade, Mohamed B.
    Emran, Ahmed A.
    Powiązania:
    https://bibliotekanauki.pl/articles/2055263.pdf
    Data publikacji:
    2022
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    integrated optics
    silicon-on-insulator waveguide
    WDM & MDM systems
    perturbation theory
    integrated optical
    devices
    hybrid modes
    guided waves
    Opis:
    On-chip optical-interconnect technology emerges as an attractive approach due to its ultra-large bandwidth and ultra-low power consumption. Silicon-on-insulator (SOI) wire waveguides, on the other hand, have been identified to potentially replace copper wires for intra-chip communication. To take advantage of the wide bandwidth of SOI waveguides, wavelengthdivision multiplexing (WDM) has been implemented. However, WDM have inherent drawbacks. Mode-division multiplexing (MDM) is a viable alternative to WDM in MIMO photonic circuits on SOI as it requires only one carrier wavelength to operate. In this vein, mode converters are key components in on-chip MDM systems. The goal of this paper is to introduce a transverse electric mode converter. The suggested device can convert fundamental transverse electric modes to first-order transverse electric ones and vice versa. It is based on small material perturbation which introduces gradual coupling between different modes. This device is very simple and highly compact; the size of which is 3 μm². Mathematical expressions for both the insertion loss and crosstalk are derived and optimized for best performance. In addition, three-dimensional finite-difference time-domain (3D-FDTD) simulations are performed in order to verify the mathematical model of the device. Our numerical results reveal that the proposed device has an insertion loss of 1.2 dB and a crosstalk of 10.1 dB. The device’s insertion loss can be decreased to 0.95 dB by adding tapers to its material perturbation.
    Źródło:
    International Journal of Electronics and Telecommunications; 2022, 68, 2; 275--280
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Design of Low–power 4-bit Flash ADC Using Multiplexer Based Encoder in 90nm CMOS Process
    Autorzy:
    Shylu Sam, D. S.
    Sam Paul, P.
    Jeba Jingle, Diana
    Mano Paul, P.
    Samuel, Judith
    Reshma, J.
    Sudeepa, P. Sarah
    Evangeline, G.
    Powiązania:
    https://bibliotekanauki.pl/articles/2124770.pdf
    Data publikacji:
    2022
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    flash ADC
    low power
    dynamic comparator
    encoder
    Opis:
    This work describes a 4-bit Flash ADC with low power consumption. The performance metrics of a Flash ADC depend on the kind of comparator and encoder used. Hence openloop comparator and mux-based encoder are used to obtain improved performance. Simulation results show that the simulated design consumes 0.265mW of power in 90nm CMOS technology using cadence-virtuoso software. The circuit operates with an operating frequency of 100MHz and a supply voltage of 1V.
    Źródło:
    International Journal of Electronics and Telecommunications; 2022, 68, 3; 565--570
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-4 z 4

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