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Wyświetlanie 1-15 z 127
Tytuł:
High-Performance Ternary (4:2) Compressor Based on Capacitive Threshold Logic
Autorzy:
Mirzaee, R. F.
Reza, A.
Powiązania:
https://bibliotekanauki.pl/articles/225977.pdf
Data publikacji:
2017
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
4:2 compressor
ternary logic
multiple-valued logic
CNFET
threshold logic
Opis:
This paper presents a ternary (4:2) compressor, which is an important component in multiplication. However, the structure differs from the binary counterpart since the ternary model does not require carry signals. The method of capacitive threshold logic (CTL) is used to achieve the output signals directly. Unlike the previously presented similar structure, the entire capacitor network is divided into two parts. This segregation results in higher reliability and robustness against unwanted process, voltage, and temperature (PVT) variations. Simulations are performed by HSPICE and 32nm CNFET technology. Simulation results demonstrate about 94% higher performance in terms of power-delay product (PDP) for the new design over the previous one.
Źródło:
International Journal of Electronics and Telecommunications; 2017, 63, 4; 355-361
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Analysis of High-Performance Near-threshold Dual Mode Logic Design
Autorzy:
Bikki, Pavankumar
Powiązania:
https://bibliotekanauki.pl/articles/226748.pdf
Data publikacji:
2019
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
CMOS logic
dual mode logic
dynamic mode
high performance
minimum energy point
near-threshold
Opis:
A novel dual mode logic (DML) model has a superior energy-performance compare to CMOS logic. The DML model has unique feature that allows switching between both modes of operation as per the real-time system requirements. The DML functions in two dissimilar modes (static and dynamic) of operation with its specific features, to selectively obtain either low-energy or high-performance. The sub-threshold region DML achieves minimum-energy. However, sub-threshold region consequence in performance is enormous. In this paper, the working of DML model in the moderate inversion region has been explored. The near-threshold region holds much of the energy saving of subthreshold designs, along with improved performance. Furthermore, robustness to supply voltage and sensitivity to the process temperature variations are presented. Monte carol analysis shows that the projected near-threshold region has minimum energy along with the moderate performance.
Źródło:
International Journal of Electronics and Telecommunications; 2019, 65, 4; 723-729
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Technology mapping oriented to adaptive logic modules
Autorzy:
Kubica, M.
Kania, D.
Powiązania:
https://bibliotekanauki.pl/articles/200466.pdf
Data publikacji:
2019
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
decomposition
logic synthesis
technology mapping
ALM
Opis:
This paper presents an innovative method of technology mapping of the circuits in ALM appearing in FPGA devices by Intel. The essence of the idea is based on using triangle tables that are connected with different configurations of blocks. The innovation of the proposed method focuses on the possibility of choosing an appropriate configuration of an ALM block, which is connected with choosing an appropriate decomposition path. The effectiveness of the proposed technique of technology mapping is proved by experiments conducted on combinational and sequential circuits.
Źródło:
Bulletin of the Polish Academy of Sciences. Technical Sciences; 2019, 67, 5; 947-956
0239-7528
Pojawia się w:
Bulletin of the Polish Academy of Sciences. Technical Sciences
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
New Conception of Safety Logic Microcontroller
Autorzy:
Sałamaj, M.
Powiązania:
https://bibliotekanauki.pl/articles/226338.pdf
Data publikacji:
2012
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
safety logic microcontroller
critical systems
master-slave architecture
handshake
GALS
conception
Opis:
In this paper a new conception of safety logic microcontroller (BML) is described, together with its physical hardware realization. The unit has various mechanisms which increase its safety and reliability, so that it can satisfy rigorous requirements of safety-critical systems. Thus, the BML unit uses some untypical and innovative technical solutions. The new approach to safety systems development allowed to propose a new conception. The paper describes also physical realization of small multiprocessor BML unit for management of decision-control systems adopted to critical usage.
Źródło:
International Journal of Electronics and Telecommunications; 2012, 58, 4; 419-424
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Application of Indexed Partition Calculus in Logic Synthesis of Boolean Functions for FPGAs
Autorzy:
Rawski, M.
Powiązania:
https://bibliotekanauki.pl/articles/226483.pdf
Data publikacji:
2011
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
indexed partition
logic synthesis
FPGA
Opis:
Functional decomposition of Boolean functions specified by cubes proved to be very efficient. Most popular decomposition methods are based on blanket calculus. However computation complexity of blanket manipulations strongly depends on number of function's variables, which prevents them from being used for large functions of many input and output variables. In this paper a new concept of indexed partition is proposed and basic operations on indexed partitions are defined. Application of this concept to logic synthesis based on functional decomposition is also discussed. The experimental results show that algorithms based on new concept are able to deliver good quality solutions even for large functions and does it many times faster than the algorithms based on blanket calculus.
Źródło:
International Journal of Electronics and Telecommunications; 2011, 57, 2; 209-216
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
SMTBDD : New Form of BDD for Logic Synthesis
Autorzy:
Kubica, M.
Kania, D.
Powiązania:
https://bibliotekanauki.pl/articles/226064.pdf
Data publikacji:
2016
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
logic synthesis
SMTBDD
decomposition
technology mapping
FPGA
digital circuits
Opis:
The main purpose of the paper is to suggest a new form of BDD - SMTBDD diagram, methods of obtaining, and its basic features. The idea of using SMTBDD diagram in the process of logic synthesis dedicated to FPGA structures is presented. The creation of SMTBDD diagrams is the result of cutting BDD diagram which is the effect of multiple decomposition. The essence of a proposed decomposition method rests on the way of determining the number of necessary ‘g’ bounded functions on the basis of the content of a root table connected with an appropriate SMTBDD diagram. The article presents the methods of searching non-disjoint decomposition using SMTBDD diagrams. Besides, it analyzes the techniques of choosing cutting levels as far as effective technology mapping is concerned. The paper also discusses the results of the experiments which confirm the efficiency of the analyzed decomposition methods.
Źródło:
International Journal of Electronics and Telecommunications; 2016, 62, 1; 33-41
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Partial Reconfiguration in the Field of Logic Controllers Design
Autorzy:
Doligalski, M.
Bukowiec, A.
Powiązania:
https://bibliotekanauki.pl/articles/227174.pdf
Data publikacji:
2013
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
HCfgPN
UML state machine diagram
Verilog
logic controller
Opis:
The paper presents method for logic controllers multi context implementation by means of partial reconfiguration. The UML state machine diagram specifies the behaviour of the logic controller. Multi context functionality is specified at the specification level as variants of the composite state. Each composite state, both orthogonal or compositional, describes specific functional requirement of the control process. The functional decomposition provided by composite states is required by the dynamic partial reconfiguration flow. The state machines specified by UML state machine diagrams are transformed into hierarchical configurable Petri nets (HCfgPN). HCfgPN are a Petri nets variant with the direct support of the exceptions handling mechanism. The paper presents placesoriented method for HCfgPN description in Verilog language. In the paper proposed methodology was illustrated by means of simple industrial control process.
Źródło:
International Journal of Electronics and Telecommunications; 2013, 59, 4; 351-356
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Experimental Comparison of Synthesis Tools Altera Quartus II and Synthagate
Autorzy:
Węgrzyn, M.
Karatkevich, A.
Powiązania:
https://bibliotekanauki.pl/articles/226665.pdf
Data publikacji:
2013
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
logic design
state machines
logic devices
FPGA
VHDL
Opis:
The paper presents comparison between efficiency of an industrial FPGA design software tool Altera Quartus II and similar design software tool Synthagate by Syntezza company of an academic origin. The experiments were performed using a series of examples describing the Mealy finite state machines; onehot state encoding was used in all cases. Area (number of used logical blocks) was the main parameter used for the comparison. Influence of the way of FSM description (in VHDL language) on the quality of synthesis was studied. The obtained results show that Synthagate in almost all cases performs synthesis more efficiently and essentially quicker than Altera Quartus. Section I presents motivation of the research. Section II reminds the notion of FSM. Section III describes problems which had to be solved to provide correctness of experimental comparison. Section IV presents some details about state encoding way used in the experiments. In Section V, the experimental results are presented. Section VI describes the problems related to the comparison which still have to be solved. Section VII presents the conclusions from the experiments. Section VIII suggests possible reasons of the detected situation.
Źródło:
International Journal of Electronics and Telecommunications; 2013, 59, 4; 357-362
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Features Reduction Using Logic Minimization Techniques
Autorzy:
Borowik, G.
Łuba, T.
Zydek, D.
Powiązania:
https://bibliotekanauki.pl/articles/227282.pdf
Data publikacji:
2012
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
machine learning
knowledge representation
discernibility function
logic minimization
attribute reduction
complement
Opis:
This paper is dedicated to two seemingly different problems. The first one concerns information theory and the second one is connected to logic synthesis methods. The reason why these issues are considered together is the important task of the efficient representation of data in information systems and as well as in logic systems. An efficient algorithm to solve the task of attributes/arguments reduction is presented.
Źródło:
International Journal of Electronics and Telecommunications; 2012, 58, 1; 71-76
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Dual synthesis of Petri net based application specific logic controllers with increased safety
Autorzy:
Tkacz, J.
Bukowiec, A.
Adamski, M.
Powiązania:
https://bibliotekanauki.pl/articles/200217.pdf
Data publikacji:
2016
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
critical safety
FPGAs
logic controllers
logic synthesis
Petri nets
verification
bezpieczeństwo krytyczne
FPGA
sterowniki logiczne
synteza logiczna
sieci Petriego
weryfikacja
Opis:
In the paper, design flow of the application specific logic controllers with increased safety by means of Petri nets is proposed. The controller architecture is based on duplicated control unit and comparison results from both units. One specification of control algorithm is used by means of Petri net for both units. The hardware duplication is obtained during dual synthesis process. This process uses two different logic synthesis methods to obtain two different hardware configurations for both control units. Additionally, the dual verification is applied to increase reliability of the control algorithm. Such design flow simplifies the process of realization of control systems with increased safety.
Źródło:
Bulletin of the Polish Academy of Sciences. Technical Sciences; 2016, 64, 3; 467-478
0239-7528
Pojawia się w:
Bulletin of the Polish Academy of Sciences. Technical Sciences
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Multi-input multi-output fuzzy logic controller for utility electric vehicle
Autorzy:
Gasbaoui, B.
Abdelkader, Ch.
Adellah, L.
Powiązania:
https://bibliotekanauki.pl/articles/141051.pdf
Data publikacji:
2011
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
pojazd elektryczny
modulacja wektora przestrzennego
sterowanie rozmyte
electric vehicle
electronic differential
space vector modulation
fuzzy logic control
multi-input multi-output fuzzy logic control
Opis:
Currently commercialization of electric vehicle (EV) is based to minimize the time of starting and acceleration. To undergo this problem multi-input multi-output fuzzy logic controller (MIMO-FLC) affect on propelled traction system forming MMS process was proposed. This paper introduces a MIMO-FLC applied on speeds of electric vehicle, the electric drive consists of two directing wheels and two rear propulsion wheels equipped with two light weight induction motors. The EV is powered by two motors of 37 kilowatts each one, delivering a 476 Nm total torque. Its high torque (476Nm) is instantly available to ensure responsive acceleration performance in built-up areas. Acceleration and steering are ensured by an electronic differential system which maintains robust control for all cases of vehicle behavior on the road. It also allows controlling independently every driving wheel to turn at different speeds in any curve. Direct torque control based on space vector modulation (DTC-SVM) is proposed to achieve the tow rear driving wheel control. The MIMO-FLC control technique is simulated in MATLAB SIMULINK environment. The simulation results have proved that the MIMO-FLC method decreases the transient oscillations and assure efficiency comportment in all type of road constraints, straight, slope, descent and curved road compared to the single input single output fuzzy controller (SISO-FLC).
Źródło:
Archives of Electrical Engineering; 2011, 60, 3; 239-256
1427-4221
2300-2506
Pojawia się w:
Archives of Electrical Engineering
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Design Protection Using Logic Encryption and Scan-Chain Obfuscation Techniques
Autorzy:
Deepak, V. A.
Priyatharishini, M.
Devi, M. Nirmala
Powiązania:
https://bibliotekanauki.pl/articles/963795.pdf
Data publikacji:
2019
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
hardware security
obfuscation
logic encryption
scan-chain
Opis:
Due to increase in threats posed by offshore foundries, the companies outsourcing IPs are forced to protect their designs from the threats posed by the foundries. Few of the threats are IP piracy, counterfeiting and reverse engineering. To overcome these, logic encryption has been observed to be a leading countermeasure against the threats faced. It introduces extra gates in the design, known as key gates which hide the functionality of the design unless correct keys are fed to them. The scan tests are used by various designs to observe the fault coverage. These scan chains can become vulnerable to side-channel attacks. The potential solution for protection of this vulnerability is obfuscation of the scan output of the scan chain. This involves shuffling the working of the cells in the scan chain when incorrect test key is fed. In this paper, we propose a method to overcome the threats posed to scan design as well as the logic circuit. The efficiency of the secured design is verified on ISCAS’89 circuits and the results prove the security of the proposed method against the threats posed.
Źródło:
International Journal of Electronics and Telecommunications; 2019, 65, 3; 389-396
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
On Transformation of a Logical Circuit to a Circuit with NAND and NOR Gates Only
Autorzy:
Baranov, S.
Karatkevich, A.
Powiązania:
https://bibliotekanauki.pl/articles/963932.pdf
Data publikacji:
2018
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
logic synthesis
logic devices
VLSI
minimization
Opis:
In the paper we consider fast transformation of a multilevel and multioutput circuit with AND, OR and NOT gates into a functionally equivalent circuit with NAND and NOR gates. The task can be solved by replacing AND and OR gates by NAND or NOR gates, which requires in some cases introducing the additional inverters or splitting the gates. In the paper the quick approximation algorithms of the circuit transformation are proposed, minimizing number of the inverters. The presented algorithms allow transformation of any multilevel circuit into a circuit being a combination of NOR gates, NAND gates or both types of universal gates.
Źródło:
International Journal of Electronics and Telecommunications; 2018, 64, 3; 373-378
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Decomposition of multi-output functions oriented to configurability of logic blocks
Autorzy:
Kubica, M.
Kania, D.
Powiązania:
https://bibliotekanauki.pl/articles/201673.pdf
Data publikacji:
2017
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
BDD
decomposition
logic synthesis
technology mapping
rozkład
Synteza logiczna
Mapowanie technologii
Opis:
The main goal of the paper is to present a logic synthesis strategy dedicated to an LUT-based FPGA. New elements of the proposed synthesis strategy include: an original method of function decomposition, non-disjoint decomposition, and technology mapping dedicated to configurability of logic blocks. The aim of all of the proposed synthesis approaches is the sharing of appropriately configured logic blocks. Innovation of the methods is based on the way of searching decomposition, which relies on multiple cutting of an MTBDD diagram describing a multi-output function. The essence of the proposed algorithms rests on the method of unicoding dedicated to sharing resources, searching non-disjoint decomposition on the basis of the partition of root tables, and choosing the levels of diagram cutting that will guarantee the best mapping to complex logic blocks. The methods mentioned above were implemented in the MultiDec tool. The efficiency of the analyzed methods was experimentally confirmed by comparing the synthesis results with both academic and commercial tools.
Źródło:
Bulletin of the Polish Academy of Sciences. Technical Sciences; 2017, 65, 3; 317-331
0239-7528
Pojawia się w:
Bulletin of the Polish Academy of Sciences. Technical Sciences
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
The hidden logic of information structure conflicts
Autorzy:
Szcześniak, Konrad
Powiązania:
https://bibliotekanauki.pl/articles/2049869.pdf
Data publikacji:
2014
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Opis:
The present paper looks at the question of Information Structure (IS) confl icts, especially in the case of Figure and Ground assignment. It is observed that in typical uses in unmarked sentences, Figure-Ground assignment runs counter to the traditional notion of Information Structure. One of the main proposals of this study is that many cases of apparently problematic IS patterns are in fact the refl ection of a two-level IS organization of sentences, where an element can bear two opposite IS values. An attempt is made to point out an experiential grounding of this double-layer organization of IS. Finally, the case of possession is examined, whose interpretation is argued to derive from the reciprocal referencing of the possessor and possessum, possible thanks to the double-layer IS and Figure-Ground assignment reversal.
Źródło:
Linguistica Silesiana; 2014, 35; 81-99
0208-4228
Pojawia się w:
Linguistica Silesiana
Dostawca treści:
Biblioteka Nauki
Artykuł
Wyświetlanie 1-15 z 127

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