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    Wyświetlanie 1-7 z 7
    Tytuł:
    A High-Efficient Low-Voltage Rectifier for CMOS Technology
    Autorzy:
    Jendernalik, W.
    Jakusz, J.
    Blakiewicz, G.
    Kłosowski, M.
    Powiązania:
    https://bibliotekanauki.pl/articles/220356.pdf
    Data publikacji:
    2016
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    CMOS rectifier
    high frequency rectifier
    wireless power transmission
    Opis:
    A new configuration of rectifier suiting CMOS technology is presented. The rectifier consists of only two n-channel MOS transistors, two capacitors and two resistors; for this reason it is very favourable in manufacturing in CMOS technology. With these features the rectifier is easy to design and cheap in production. Despite its simplicity, the rectifier has relatively good characteristics, the voltage and power efficiency, and bandwidth greater than 89%, 87%, and 1 GHz, respectively. The performed simulations and measurements of a prototype circuit fully confirmed its correct operation and advantages.
    Źródło:
    Metrology and Measurement Systems; 2016, 23, 2; 261-268
    0860-8229
    Pojawia się w:
    Metrology and Measurement Systems
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    64 channel neural recording amplifier with tunable bandwidth in 180 nm CMOS technology
    Autorzy:
    Gryboś, P.
    Kmon, P.
    Żołądź, M.
    Szczygieł, R.
    Kachel, M.
    Lewandowski, M.
    Błasiak, T.
    Powiązania:
    https://bibliotekanauki.pl/articles/220527.pdf
    Data publikacji:
    2011
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    neurobiological measurements
    low noise amplifier
    neural recording
    band-pass filter
    multichannel ASIC
    Opis:
    This paper presents the design and measurements of low-noise multichannel front-end electronics for recording extra-cellular neuronal signals using microelectrode arrays. The integrated circuit contains 64 readout channels and is fabricated in CMOS 180 nm technology. A single readout channel is built of an AC coupling circuit at the input, a low-noise preamplifier, a band-pass filter and a second amplifier. In order to reduce the number of output lines, the 64 analog signals from readout channels are multiplexed to a single output by an analog multiplexer. The chip is optimized for low noise and good matching performance and has the possibility of passband tuning. The low cut-off frequency can be tuned in the 1 Hz - 60 Hz range while the high cut-off frequency can be tuned in the 3.5 kHz - 15 kHz range. For the nominal gain setting at 44 dB and power dissipation per single channel of 220 žW, the equivalent input noise is in the range from 6 žV - 11 žV rms depending on the band-pass filter settings. The chip has good uniformity concerning the spread of its electrical parameters from channel to channel. The spread of the gain calculated as standard deviation to mean value is about 4.4% and the spread of the low cut-off frequency set at 1.6 Hz is only 0.07 Hz. The chip occupies 5×2.3 mm⊃2 of silicon area. To our knowledge, our solution is the first reported multichannel recording system which allows to set in each recording channel the low cut-off frequency within a single Hz with a small spread of this parameter from channel to channel. The first recordings of action potentials from the thalamus of the rat under urethane anesthesia are presented.
    Źródło:
    Metrology and Measurement Systems; 2011, 18, 4; 631-643
    0860-8229
    Pojawia się w:
    Metrology and Measurement Systems
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Design of a nanoswitch in 130 nm CMOS technology for 2.4 GHz wireless terminals
    Autorzy:
    Bhuiyan, M. A.
    Reaz, M. B. I.
    Jalil, J.
    Rahman, L. F.
    Powiązania:
    https://bibliotekanauki.pl/articles/200508.pdf
    Data publikacji:
    2014
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    CMOS
    ISM band
    nanometer
    transceivers
    T/R switch
    wireless
    Opis:
    This paper proposes a transmit/receive (T/R) nanoswitch in 130 nm CMOS technology for 2.4 GHz ISM band transceivers. It exhibits 1.03-dB insertion loss, 27.57-dB isolation and a power handling capacity (P1 dB) of 36.2-dBm. It dissipates only 6.87 μW power for 1.8/0 V control voltages and is capable of switching in 416.61 ps. Besides insertion loss and isolation of the nanoswitch is found to vary by 0.1 dB and 0.9 dB, respectively for a temperature change of 125°C. Only the transistor W/L optimization and resistive body floating technique is used for such lucrative performances. Besides absence of bulky inductors and capacitors in the schematic circuit help to attain the smallest chip area of 0.0071 mm2 which is the lowest ever reported in this frequency band. Therefore, simplicity and low chip area of the circuit trim down the cost of fabrication without compromising the performance issue.
    Źródło:
    Bulletin of the Polish Academy of Sciences. Technical Sciences; 2014, 62, 2; 399-406
    0239-7528
    Pojawia się w:
    Bulletin of the Polish Academy of Sciences. Technical Sciences
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Characteristics of an image sensor with early-vision processing fabricated in standard 0.35 žm CMOS technology
    Autorzy:
    Jendernalik, W.
    Jakusz, J.
    Blakiewicz, G.
    Szczepański, S.
    Piotrowski, R.
    Powiązania:
    https://bibliotekanauki.pl/articles/220599.pdf
    Data publikacji:
    2012
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    CMOS imager
    analogue processor array
    smart sensor
    vision chip
    Opis:
    The article presents measurement results of prototype integrated circuits for acquisition and processing of images in real time. In order to verify a new concept of circuit solutions of analogue image processors, experimental integrated circuits were fabricated. The integrated circuits, designed in a standard 0.35 žm CMOS technology, contain the image sensor and analogue processors that perform low-level convolution-based image processing algorithms. The prototype with a resolution of 32 x 32 pixels allows the acquisition and processing of images at high speed, up to 2000 frames/s. Operation of the prototypes was verified in practice using the developed software and a measurement system based on a FPGA platform.
    Źródło:
    Metrology and Measurement Systems; 2012, 19, 2; 191-202
    0860-8229
    Pojawia się w:
    Metrology and Measurement Systems
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    A 1.67 pJ/Conversion-step 8-bit SAR-Flash ADC Architecture in 90-nm CMOS Technology
    Autorzy:
    Khatak, Anil
    Kumar, Manoj
    Dhull, Sanjeev
    Powiązania:
    https://bibliotekanauki.pl/articles/1844527.pdf
    Data publikacji:
    2021
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    analog to digital converter
    ADC
    successive approximation register (SAR)
    common mode current feedback gain boosting
    CMFD-GB
    residue amplifier
    RA
    spurious free dynamic range
    SFDR
    integral nonlinearity
    INL
    differential nonlinearity
    DNL
    Opis:
    A novice advanced architecture of 8-bit analog to digital converter is introduced and analyzed in this paper. The structure of proposed ADC is based on the sub-ranging ADC architecture in which a 4-bit resolution flash-ADC is utilized. The proposed ADC architecture is designed by employing a comparator which is equipped with common mode current feedback and gain boosting technique (CMFD-GB) and a residue amplifier. The proposed 8 bits ADC structure can achieve the speed of 140 mega-samples per second. The proposed ADC architecture is designed at a resolution of 8 bits at 10 MHz sampling frequency. DNL and INL values of the proposed design are -0.94/1.22 and -1.19/1.19 respectively. The ADC design dissipates a power of 1.24 mW with the conversion speed of 0.98 ns. The magnitude of SFDR and SNR from the simulations at Nyquist input is 39.77 and 35.62 decibel respectively. Simulations are performed on a SPICE based tool in 90 nm CMOS technology. The comparison shows better performance for this proposed ADC design in comparison to other ADC architectures regarding speed, resolution and power consumption.
    Źródło:
    International Journal of Electronics and Telecommunications; 2021, 67, 3; 347-354
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Multiple output CMOS current amplifier
    Autorzy:
    Pankiewicz, B.
    Powiązania:
    https://bibliotekanauki.pl/articles/201141.pdf
    Data publikacji:
    2016
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    current amplifier
    current follower
    current mirror
    CMOS technology
    wzmacniacz prądowy
    prąd
    technologia CMOS
    Opis:
    In this paper the multiple output current amplifier basic cell is proposed. The triple output current mirror and current follower circuit are described in detail. The cell consists of a split nMOS differential pair and accompanying biasing current sources. It is suitable for low voltage operation and exhibits highly linear DC response. Through cell devices scaling, not only unity, but also any current gains are achievable. As examples, a current amplifier and bandpass biquad section designed in CMOS TSMC 90nm technology are presented. The current amplifier is powered from a 1.2V supply. MOS transistors scaling was chosen to obtain output gains equal to -2, 1 and 2. Simulated real gains are -1.941, 0.966 and 1.932 respectively. The 3dB passband obtained is above 20MHz, while current consumption is independent of input and output currents and is only 7.77μA. The bandpass biquad section utilises the previously presented amplifier, two capacitors and one resistor, and has a Q factor equal to 4 and pole frequency equal to 100 kHz.
    Źródło:
    Bulletin of the Polish Academy of Sciences. Technical Sciences; 2016, 64, 2; 301-306
    0239-7528
    Pojawia się w:
    Bulletin of the Polish Academy of Sciences. Technical Sciences
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Designing Method of Compact n-to-2ⁿ Decoders
    Autorzy:
    Brzozowski, I.
    Zachara, Ł.
    Kos, A.
    Powiązania:
    https://bibliotekanauki.pl/articles/226116.pdf
    Data publikacji:
    2013
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    decoder
    address decoder
    standard cell
    layouts design
    CMOS technology
    power dissipation
    power consumption
    delay
    Opis:
    What decoder is, everyone knows. The paper presents fast and efficient method of layouts design of n-to-2ⁿ -lines decoders. Two scenarios of layout arrangement are proposed and described. Based on a few building blocks only, especially prepared, and appropriate procedure of their placement, a decoder of any size can be build. Layouts of all needed fundamental blocks were designed in CMOS technology, as standard library. Moreover, some important parameters, such area, power dissipation and delay, were assessed and compared for decoders designed with proposed method and traditional. Power consumption were considered under extended model, which takes into account changes of input vectors, not only switching activity factor. All designs were done in UMC 180 CMOS technology.
    Źródło:
    International Journal of Electronics and Telecommunications; 2013, 59, 4; 405-413
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-7 z 7

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