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Wyszukujesz frazę "pipelining" wg kryterium: Temat


Wyświetlanie 1-2 z 2
Tytuł:
Pipelined division of signed numbers with the use of residue arithmetic for small number range with the programmable gate array
Autorzy:
Smyk, R.
Ulman, Z.
Czyżak, M.
Powiązania:
https://bibliotekanauki.pl/articles/376378.pdf
Data publikacji:
2013
Wydawca:
Politechnika Poznańska. Wydawnictwo Politechniki Poznańskiej
Tematy:
pipelining
residue number system
RNS
residue arithmetic
Opis:
In this work an architecture of the pipelined signed residue divider for the small number range is presented. Its operation is based on reciprocal calculation and multiplication by the dividend. The divisor in the signed binary form is used to compute the approximated reciprocal in the residue form by the table look-up. In order to limit the look-up table address an algoritm based on segmentation of the divisor into two segments is used. The approximate reciprocal transformed to residue representation with the proper sign is stored in look-up tables. During operation it is multiplied by the dividend in the residue form and subsequently scaled. The pipelined realization of the divider in the FPGA environment is also shown.
Źródło:
Poznan University of Technology Academic Journals. Electrical Engineering; 2013, 76; 117-126
1897-0737
Pojawia się w:
Poznan University of Technology Academic Journals. Electrical Engineering
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Pipelined scaling of signed residue numbers with the mixed-radix conversion in the programmable gate array
Autorzy:
Czyżak, M.
Smyk, R.
Ulman, Z.
Powiązania:
https://bibliotekanauki.pl/articles/377373.pdf
Data publikacji:
2013
Wydawca:
Politechnika Poznańska. Wydawnictwo Politechniki Poznańskiej
Tematy:
scaling technique
Mixed-Radix System
MRS
Residue Number System
pipelining
Opis:
In this work a scaling technique of signed residue numbers is proposed. The method is based on conversion to the Mixed-Radix System(MRS) adapted for the FPGA implementation. The scaling factor is assumed to be a moduli product from the Residue Number System (RNS) base. Scaling is performed by scaling of terms of the mixed-radix expansion, generation of residue representations of scaled terms, binary addition of these representations and generation of residues for all moduli. The sign is detected on the basis of the value of the most significant coefficient of the MRS representation. For negative numbers their residues are adequately corrected. The basic blocks of the scaler are realized in the form of the modified two-operand modulo adders with included additional multiply and modulo reduction operations. The pipelined realization of the scaler in the Xilinx environment is shown and analyzed with respect to hardware amount and maximum pipelining frequency. The design is based on the LUTs(26x 1) that simulate small RAMs serving as the main component for the look-up realization.
Źródło:
Poznan University of Technology Academic Journals. Electrical Engineering; 2013, 76; 89-99
1897-0737
Pojawia się w:
Poznan University of Technology Academic Journals. Electrical Engineering
Dostawca treści:
Biblioteka Nauki
Artykuł
    Wyświetlanie 1-2 z 2

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