- Tytuł:
- A low-jitter, full-differential PLL in 0.18μm CMOS technology
- Autorzy:
-
Modarresi, F.
Ghasemzadeh, M.
Mazlumi, M.
Amini, A.
Abolfathi, T. - Powiązania:
- https://bibliotekanauki.pl/articles/397765.pdf
- Data publikacji:
- 2016
- Wydawca:
- Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
- Tematy:
-
full differential PLL
PFD
VCO
low jitter
CPL
pętla synchronizacji fazy
PLL
generator sterowany napięciem
niski jitter - Opis:
- This paper presents a Phase Locked Loop (PLL) which works with minimum jitter in the operation frequency range of 600MHZ to 900MHZ. Utilizing a full differential architecture that consists of several blocks of differential VCO, a differential PFD and a differential CPL leads to limiting the RMS jitter to 4.06ps, with 50mV power supply noise in the frequency range of 750MHz. Simulation results using 0.18μm CMOS TSMC standard technology demonstrate the power-consumption of 4.6mW at the supply voltage of 1.8V.
- Źródło:
-
International Journal of Microelectronics and Computer Science; 2016, 7, 4; 119-122
2080-8755
2353-9607 - Pojawia się w:
- International Journal of Microelectronics and Computer Science
- Dostawca treści:
- Biblioteka Nauki
Artykuł