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Wyszukujesz frazę "wafer" wg kryterium: Temat


Wyświetlanie 1-3 z 3
Tytuł:
Detection of Monocrystalline Silicon Wafer Defects Using Deep Transfer Learning
Autorzy:
Ganum, Adriana
Iskandar, D. N. F. Awang
Chin, Lim Phei
Fauzi, Ahmad Hadinata
Powiązania:
https://bibliotekanauki.pl/articles/2058502.pdf
Data publikacji:
2022
Wydawca:
Instytut Łączności - Państwowy Instytut Badawczy
Tematy:
automated optical inspection
machine learning
neural network
wafer imperfection identification
Opis:
Defect detection is an important step in industrial production of monocrystalline silicon. Through the study of deep learning, this work proposes a framework for classifying monocrystalline silicon wafer defects using deep transfer learning (DTL). An existing pre-trained deep learning model was used as the starting point for building a new model. We studied the use of DTL and the potential adaptation of Mo bileNetV2 that was pre-trained using ImageNet for extracting monocrystalline silicon wafer defect features. This has led to speeding up the training process and to improving performance of the DTL-MobileNetV2 model in detecting and classifying six types of monocrystalline silicon wafer defects (crack, double contrast, hole, microcrack, saw-mark and stain). The process of training the DTL-MobileNetV2 model was optimized by relying on the dense block layer and global average pooling (GAP) method which had accelerated the convergence rate and improved generalization of the classification network. The monocrystalline silicon wafer defect classification technique relying on the DTL-MobileNetV2 model achieved the accuracy rate of 98.99% when evaluated against the testing set. This shows that DTL is an effective way of detecting different types of defects in monocrystalline silicon wafers, thus being suitable for minimizing misclassification and maximizing the overall production capacities.
Źródło:
Journal of Telecommunications and Information Technology; 2022, 1; 34--42
1509-4553
1899-8852
Pojawia się w:
Journal of Telecommunications and Information Technology
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Analysis of errors in on-wafer measurements due to multimode propagation in CB-CPW
Autorzy:
Lewandowski, A.
Wiatr, W.
Powiązania:
https://bibliotekanauki.pl/articles/307779.pdf
Data publikacji:
2005
Wydawca:
Instytut Łączności - Państwowy Instytut Badawczy
Tematy:
on-wafer measurements
multimode propagation
error analysis
conductor-backed coplanar waveguide (CB-CPW)
microstrip-like mode
numerical electromagnetic analysis
on-wafer probe
calibration
de-embedding
monolithic microwave integrated circuit (MMIC)
Opis:
We study for the first time errors in on-wafer scattering parameter measurements caused by the parasitic microstrip-like mode propagation in conductor-backed coplanar waveguide (CB-CPW). We determine upper bound for these errors for typical CPW devices such as a matched load, an open circuit, and a transmission line section. To this end, we develop an electromagnetic-simulations-based multimode three-port model for the transition between an air-coplanar probe and the CB-CPW. Subsequently, we apply this model to examine errors in the device S parameters de-embedded from measurements affected by the parasitic MSL mode. Our analysis demonstrates that the multimode propagation in CB-CPW may significantly deteriorate the S-parameters measured on wafer.
Źródło:
Journal of Telecommunications and Information Technology; 2005, 2; 16-22
1509-4553
1899-8852
Pojawia się w:
Journal of Telecommunications and Information Technology
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Variation Analysis of CMOS Technologies Using Surface-Potential MOSFET Model
Autorzy:
Mattausch, H. J.
Yumisaki, A.
Sadachika, N.
Kaya, A.
Johguchi, K.
Koide, T.
Miura-Mattausch, M.
Powiązania:
https://bibliotekanauki.pl/articles/308251.pdf
Data publikacji:
2009
Wydawca:
Instytut Łączności - Państwowy Instytut Badawczy
Tematy:
compact model
fabrication inaccuracy
field-effect transistor
macroscopic
microscopic
potential at channel surface
silicon
within wafer
Opis:
An analysis of the measured macroscopic withinwafer variations for threshold voltage (Vth) and on-current (Ion) over several technology generations (180 nm, 100 nm and 65 nm) is reported. It is verified that the dominant microscopic variations of the MOSFET device can be extracted quantitatively from these macroscopic variation data by applying the surface-potential compact model Hiroshima University STARC IGFET model 2 (HiSIM2), which is presently brought into industrial application. Only a small number of microscopic parameters, representing substrate doping (NSUBC), pocket-implantation doping (NSUBP), carrier-mobility degradation due to gate-interface roughness (MUESR1) and channel-length variation during the gate formation (XLD) are found sufficient to quantitatively reproduce the measured macroscopic within-wafer variations of Vth and Ion for all channel length Lg and all technology generations. Quantitative improvements from 180 nm to 65 nm are confirmed to be quite large for MUESR1 (about 70%) and Lmin(XLD) (55%) variations, related to the gate-oxide interface and the gate-stack structuring, respectively. On the other hand, doping-related technology advances, which are reflected by the variation magnitudes of NSUBC (30%) and NSUBP (25%), are found to be considerably smaller. Furthermore, specific combinations of extreme microscopic parameter-variation values are able to represent the boundaries of macroscopic fabrication inaccuracies for Vth and Ion. These combinations are found to remain identical, not only for all Lg of a given technology node, but also for all investigated technologies with minimum Lg of 180 nm, 100 nm and 65 nm.
Źródło:
Journal of Telecommunications and Information Technology; 2009, 4; 37-44
1509-4553
1899-8852
Pojawia się w:
Journal of Telecommunications and Information Technology
Dostawca treści:
Biblioteka Nauki
Artykuł
    Wyświetlanie 1-3 z 3

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