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Wyświetlanie 1-4 z 4
Tytuł:
Wearable biosensing: signal processing and communication architectures issues
Autorzy:
Celka, P.
Vetter, R.
Renevey, P.
Verjus, C.
Neuman, V.
Luprano, J.
Decotignie, J. D.
Piguet, C.
Powiązania:
https://bibliotekanauki.pl/articles/309491.pdf
Data publikacji:
2005
Wydawca:
Instytut Łączności - Państwowy Instytut Badawczy
Tematy:
wearable sensors
wireless BAN
biosignal processing
low-power DSP
Opis:
Long-term monitoring of human vital signs is becoming one of the most important fields of research of biomedical engineering. In order to achieve weeks to months of monitoring, new strategies for sensing, conditioning, processing and communication have to be developed. Several strategies are emerging and show different possible architectures. This paper essentially focuses on issues in wearable biosignal processing and communication architecture currently running at the Swiss Center for Electronics and Microtechnology (CSEM) in the framework of several European projects.
Źródło:
Journal of Telecommunications and Information Technology; 2005, 4; 90-104
1509-4553
1899-8852
Pojawia się w:
Journal of Telecommunications and Information Technology
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Multiobjective Design of Wireless Ad Hoc Networks: Security, Real-Time and Lifetime
Autorzy:
Zdravko, K.
Powiązania:
https://bibliotekanauki.pl/articles/308972.pdf
Data publikacji:
2009
Wydawca:
Instytut Łączności - Państwowy Instytut Badawczy
Tematy:
ad hoc networks
low-power routing
multihop communication
secure routing
Opis:
This paper deals with the tradeoffs between security, real-time and lifetime performance. Due to the multihop nature of communication wireless ad hoc networks are very vulnerable to attacks. Malicious nodes included in a routing path may misbehave and organize attacks such as black holes. Scaling the number of hops for a packet delivery we trade off energy efficiency against security and real-time communication. To study the multihop communication we propose a hierarchical communication model. The REWARD (receive, watch, redirect) algorithm for secure routing is employed as a main example for corrective actions. Symmetrical routing is a distinguish feature of protocols such as REWARD and we outline the threshold of conflict between power-efficient partitioning of communication links and symmetrical routing.
Źródło:
Journal of Telecommunications and Information Technology; 2009, 2; 13-21
1509-4553
1899-8852
Pojawia się w:
Journal of Telecommunications and Information Technology
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
A Comparative Study of Single- and Dual-Threshold Voltage SRAM Cells
Autorzy:
Kushwaha, P.
Chaudhry, A.
Powiązania:
https://bibliotekanauki.pl/articles/308384.pdf
Data publikacji:
2011
Wydawca:
Instytut Łączności - Państwowy Instytut Badawczy
Tematy:
5T SRAM
65 nm CMOS technology
6T SRAM
7T SRAM
low power SRAM
power reduction technique
Opis:
In this paper, a comparison has been drawn between 5 transistor (5T), 6T and 7T SRAM cells. All the cells have been designed using both single-threshold (conventional) and dual-threshold (dual-Vt) voltage techniques. Their respective delays and power consumption have been calculated at 180 nm and 65 nm CMOS technology. With technology scaling, power consumption decreases by 80% to 90%, with some increase in write time because of the utilization of high- Vt transistors in write critical path. The results show that the read delay of 7T SRAM cell is 9% lesser than 5T SRAM cell and 29% lesser than 6T SRAM cell due to the lower resistance of the read access delay path. While read power of 5T SRAM cell is reduced by 10% and 24% as compared to 7T SRAM, 6T SRAM cell respectively. The write speed, however, is degraded by 1% to 3% with the 7T and 5T SRAM cells as compared to the 6T SRAM cells due to the utilization of single ended architecture. While write power of 5T SRAM cell is reduced by up to 40% and 67% as compared to 7T SRAM, 6T SRAM cell respectively.
Źródło:
Journal of Telecommunications and Information Technology; 2011, 4; 124-130
1509-4553
1899-8852
Pojawia się w:
Journal of Telecommunications and Information Technology
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Advanced compact modeling of the deep submicron technologies
Autorzy:
Grabiński, W.
Bucher, M.
Sallese, J.-M.
Krummenacher, F.
Powiązania:
https://bibliotekanauki.pl/articles/309312.pdf
Data publikacji:
2000
Wydawca:
Instytut Łączności - Państwowy Instytut Badawczy
Tematy:
ultra deep submicron (UDSM) technology
compact modeling
EKV MOS transistor model
MOSFET
matching
low power
RF applications
Opis:
The technology of CMOS large-scale integrated circuits (LSI's) achieved remarkable advances over last 25 year and the progress is expected to continue well into the next century. The progress has been driven by the downsizing of the active devices such as MOSFETs. Approaching these dimensions, MOSFET characteristics cannot be accurately predicted using classical modeling methods currently used in the most common MOSFET models such as BSIM, MM9 etc, without introducing large number of empirical parameters. Various physical effects that needed to be considered while modeling UDSM devices: quantization of the inversion layer, mobility degradation, carrier velocity saturation and overshoot, polydepletion effects, bias dependent source/drain resistances and capacitances, vertical and lateral doping profiles, etc. In this paper, we will discuss the progress in the CMOS technology and the anticipated difficulties of the sub-0.25 žm LSI downsizing. Subsequently, basic MOSFET modeling methodologies that are more appropriate for UDSM MOSFETs will be presented as well. The advances in compact MOSFET devices will be illustrated using application examples of the EPFL EKV model
Źródło:
Journal of Telecommunications and Information Technology; 2000, 3-4; 31-42
1509-4553
1899-8852
Pojawia się w:
Journal of Telecommunications and Information Technology
Dostawca treści:
Biblioteka Nauki
Artykuł
    Wyświetlanie 1-4 z 4

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