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    Wyświetlanie 1-4 z 4
    Tytuł:
    Ultrathin oxynitride films for CMOS technology
    Autorzy:
    Beck, R.B.
    Jakubowski, A.
    Powiązania:
    https://bibliotekanauki.pl/articles/308025.pdf
    Data publikacji:
    2004
    Wydawca:
    Instytut Łączności - Państwowy Instytut Badawczy
    Tematy:
    MOS technology
    gate stack
    ultrathin oxynitride layers
    high temperature processing
    plasma processing
    Opis:
    In this work, a review of possible methods of oxynitride film formation will be given. These are different combinations of methods applying high-temperature oxidation and nitridation, as well as ion implantation and deposition techniques. The layers obtained using these methods differ, among other aspects in: nitrogen content, its profile across the ultrathin layer,... etc., which have considerable impact on device properties, such as leakage current, channel mobility, device stability and its reliability. Unlike high-temperature processes, which (understood as a single process step) usually do not allow the control of the nitrogen content at the silicon-oxynitride layer interface, different types of deposition techniques allow certain freedom in this respect. However, deposition techniques have been believed for many years not to be suitable for such a responsible task as the formation of gate dielectrics in MOS devices. Nowadays, this belief seems unjustified. On the contrary, these methods often allow the formation of the layers not only with a uniquely high content of nitrogen but also a very unusual nitrogen profile, both at exceptionally low temperatures. This advantage is invaluable in the times of tight restrictions imposed on the thermal budget (especially for high performance devices). Certain specific features of these methods also allow unique solutions in certain technologies (leading to simplifications of the manufacturing process and/or higher performance and reliability), such as dual gate technology for system-on-chip (SOC) manufacturing.
    Źródło:
    Journal of Telecommunications and Information Technology; 2004, 1; 62-69
    1509-4553
    1899-8852
    Pojawia się w:
    Journal of Telecommunications and Information Technology
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    TSSOI as an efficient tool for diagnostics of SOI technology in Institute of Electron Technology
    Autorzy:
    Barański, M.
    Domański, K.
    Grabiec, P.
    Grodner, M.
    Jaroszewicz, B.
    Kociubiński, A.
    Kucewicz, W.
    Kucharski, K.
    Marczewski, J.
    Niemiec, H.
    Sapor, M.
    Tomaszewski, D.
    Powiązania:
    https://bibliotekanauki.pl/articles/308825.pdf
    Data publikacji:
    2005
    Wydawca:
    Instytut Łączności - Państwowy Instytut Badawczy
    Tematy:
    SOI CMOS technology
    pixel detector
    test structure
    Opis:
    This paper reports a test structure for characterization of a new technology combining a standard CMOS process with pixel detector manufacturing technique. These processes are combined on a single thick-_lm SOI wafer. Preliminary results of the measurements performed on both MOS SOI transistors and dedicated SOI test structures are described in detail.
    Źródło:
    Journal of Telecommunications and Information Technology; 2005, 1; 85-93
    1509-4553
    1899-8852
    Pojawia się w:
    Journal of Telecommunications and Information Technology
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    A Comparative Study of Single- and Dual-Threshold Voltage SRAM Cells
    Autorzy:
    Kushwaha, P.
    Chaudhry, A.
    Powiązania:
    https://bibliotekanauki.pl/articles/308384.pdf
    Data publikacji:
    2011
    Wydawca:
    Instytut Łączności - Państwowy Instytut Badawczy
    Tematy:
    5T SRAM
    65 nm CMOS technology
    6T SRAM
    7T SRAM
    low power SRAM
    power reduction technique
    Opis:
    In this paper, a comparison has been drawn between 5 transistor (5T), 6T and 7T SRAM cells. All the cells have been designed using both single-threshold (conventional) and dual-threshold (dual-Vt) voltage techniques. Their respective delays and power consumption have been calculated at 180 nm and 65 nm CMOS technology. With technology scaling, power consumption decreases by 80% to 90%, with some increase in write time because of the utilization of high- Vt transistors in write critical path. The results show that the read delay of 7T SRAM cell is 9% lesser than 5T SRAM cell and 29% lesser than 6T SRAM cell due to the lower resistance of the read access delay path. While read power of 5T SRAM cell is reduced by 10% and 24% as compared to 7T SRAM, 6T SRAM cell respectively. The write speed, however, is degraded by 1% to 3% with the 7T and 5T SRAM cells as compared to the 6T SRAM cells due to the utilization of single ended architecture. While write power of 5T SRAM cell is reduced by up to 40% and 67% as compared to 7T SRAM, 6T SRAM cell respectively.
    Źródło:
    Journal of Telecommunications and Information Technology; 2011, 4; 124-130
    1509-4553
    1899-8852
    Pojawia się w:
    Journal of Telecommunications and Information Technology
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Applying shallow nitrogen implantation from rf plasma for dual gate oxide technology
    Autorzy:
    Bieniek, T.
    Beck, R. B.
    Jakubowski, A.
    Głuszko, G.
    Konarski, P.
    Ćwil, M.
    Powiązania:
    https://bibliotekanauki.pl/articles/308685.pdf
    Data publikacji:
    2007
    Wydawca:
    Instytut Łączności - Państwowy Instytut Badawczy
    Tematy:
    CMOS
    dual gate oxide
    gate stack
    oxynitride
    plasma implantation
    Opis:
    The goal of this work was to study nitrogen implantation from plasma with the aim of applying it in dual gate oxide technology and to examine the influence of the rf power of plasma and that of oxidation type. The obtained structures were examined by means of ellipsometry, SIMS and electrical characterization methods.
    Źródło:
    Journal of Telecommunications and Information Technology; 2007, 3; 3-8
    1509-4553
    1899-8852
    Pojawia się w:
    Journal of Telecommunications and Information Technology
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-4 z 4

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