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    Wyświetlanie 1-3 z 3
    Tytuł:
    A High-Efficient Low-Voltage Rectifier for CMOS Technology
    Autorzy:
    Jendernalik, W.
    Jakusz, J.
    Blakiewicz, G.
    Kłosowski, M.
    Powiązania:
    https://bibliotekanauki.pl/articles/220356.pdf
    Data publikacji:
    2016
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    CMOS rectifier
    high frequency rectifier
    wireless power transmission
    Opis:
    A new configuration of rectifier suiting CMOS technology is presented. The rectifier consists of only two n-channel MOS transistors, two capacitors and two resistors; for this reason it is very favourable in manufacturing in CMOS technology. With these features the rectifier is easy to design and cheap in production. Despite its simplicity, the rectifier has relatively good characteristics, the voltage and power efficiency, and bandwidth greater than 89%, 87%, and 1 GHz, respectively. The performed simulations and measurements of a prototype circuit fully confirmed its correct operation and advantages.
    Źródło:
    Metrology and Measurement Systems; 2016, 23, 2; 261-268
    0860-8229
    Pojawia się w:
    Metrology and Measurement Systems
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    64 channel neural recording amplifier with tunable bandwidth in 180 nm CMOS technology
    Autorzy:
    Gryboś, P.
    Kmon, P.
    Żołądź, M.
    Szczygieł, R.
    Kachel, M.
    Lewandowski, M.
    Błasiak, T.
    Powiązania:
    https://bibliotekanauki.pl/articles/220527.pdf
    Data publikacji:
    2011
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    neurobiological measurements
    low noise amplifier
    neural recording
    band-pass filter
    multichannel ASIC
    Opis:
    This paper presents the design and measurements of low-noise multichannel front-end electronics for recording extra-cellular neuronal signals using microelectrode arrays. The integrated circuit contains 64 readout channels and is fabricated in CMOS 180 nm technology. A single readout channel is built of an AC coupling circuit at the input, a low-noise preamplifier, a band-pass filter and a second amplifier. In order to reduce the number of output lines, the 64 analog signals from readout channels are multiplexed to a single output by an analog multiplexer. The chip is optimized for low noise and good matching performance and has the possibility of passband tuning. The low cut-off frequency can be tuned in the 1 Hz - 60 Hz range while the high cut-off frequency can be tuned in the 3.5 kHz - 15 kHz range. For the nominal gain setting at 44 dB and power dissipation per single channel of 220 žW, the equivalent input noise is in the range from 6 žV - 11 žV rms depending on the band-pass filter settings. The chip has good uniformity concerning the spread of its electrical parameters from channel to channel. The spread of the gain calculated as standard deviation to mean value is about 4.4% and the spread of the low cut-off frequency set at 1.6 Hz is only 0.07 Hz. The chip occupies 5×2.3 mm⊃2 of silicon area. To our knowledge, our solution is the first reported multichannel recording system which allows to set in each recording channel the low cut-off frequency within a single Hz with a small spread of this parameter from channel to channel. The first recordings of action potentials from the thalamus of the rat under urethane anesthesia are presented.
    Źródło:
    Metrology and Measurement Systems; 2011, 18, 4; 631-643
    0860-8229
    Pojawia się w:
    Metrology and Measurement Systems
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Characteristics of an image sensor with early-vision processing fabricated in standard 0.35 žm CMOS technology
    Autorzy:
    Jendernalik, W.
    Jakusz, J.
    Blakiewicz, G.
    Szczepański, S.
    Piotrowski, R.
    Powiązania:
    https://bibliotekanauki.pl/articles/220599.pdf
    Data publikacji:
    2012
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    CMOS imager
    analogue processor array
    smart sensor
    vision chip
    Opis:
    The article presents measurement results of prototype integrated circuits for acquisition and processing of images in real time. In order to verify a new concept of circuit solutions of analogue image processors, experimental integrated circuits were fabricated. The integrated circuits, designed in a standard 0.35 žm CMOS technology, contain the image sensor and analogue processors that perform low-level convolution-based image processing algorithms. The prototype with a resolution of 32 x 32 pixels allows the acquisition and processing of images at high speed, up to 2000 frames/s. Operation of the prototypes was verified in practice using the developed software and a measurement system based on a FPGA platform.
    Źródło:
    Metrology and Measurement Systems; 2012, 19, 2; 191-202
    0860-8229
    Pojawia się w:
    Metrology and Measurement Systems
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-3 z 3

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