Temat: GATE - Katalog OPAC zbiorów

Skocz do pozycji: 1.

Tytuł:: Applying shallow nitrogen implantation from rf plasma for dual gate oxide technology
Autorzy:: Bieniek, T.
Beck, R. B.
Jakubowski, A.
Głuszko, G.
Konarski, P.
Ćwil, M.
Powiązania:: https://bibliotekanauki.pl/articles/308685.pdf
Data publikacji:: 2007
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: CMOS
dual gate oxide
gate stack
oxynitride
plasma implantation
Opis:: The goal of this work was to study nitrogen implantation from plasma with the aim of applying it in dual gate oxide technology and to examine the influence of the rf power of plasma and that of oxidation type. The obtained structures were examined by means of ellipsometry, SIMS and electrical characterization methods.
Źródło:: Journal of Telecommunications and Information Technology; 2007, 3; 3-8
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 2.

Tytuł:: Challenges in scaling of CMOS devices towards 65 nm node
Autorzy:: Jurczak, M.
Veloso, A.
Rooyackers, R.
Augendre, E.
Mertens, S.
Rotschild, A.
Scaekers, M.
Lindsay, R.
Lauwers, A.
Henson, K.
Severi, S.
Pollentier, I.
Keersgieter de, A.
Powiązania:: https://bibliotekanauki.pl/articles/308984.pdf
Data publikacji:: 2005
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: CMOS devices
gate dielectrics
shallow junctions
silicide
gate stack
lithography
gate patterning
silicon recess
device integration
Opis:: The current trend in scaling transistor gate length below 60 nm is posing great challenges both related to process technology and circuit/system design. From the process technology point of view it is becoming increasingly difficult to continue scaling in traditional way due to fundamental limitations like resolution, quantum effects or random fluctuations. In turn, this has an important impact on electrical device specifications especially leakage current and the circuit power dissipation.
Źródło:: Journal of Telecommunications and Information Technology; 2005, 1; 3-6
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 3.

Tytuł:: Special size effects in advanced single-gate and multiple-gate SOI transistors
Autorzy:: Ohata, A.
Ritzenthaler, R.
Faynot, O.
Cristoloveanu, S.
Powiązania:: https://bibliotekanauki.pl/articles/308994.pdf
Data publikacji:: 2007
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: MOSFET
SOI
ultra-thin silicon
multiple-gate
mobility
coupling effect
thin gate oxide
gate-induced floating body effect
drain-induced virtual substrate biasing
Opis:: State-of-the-art SOI transistors require a very small body. This paper examines the effects of body thinning and thin-gate oxide in SOI MOSFETs on their electrical characteristics. In particular, the influence of film thickness on the interface coupling and carrier mobility is discussed. Due to coupling, the separation between the front and back channels is difficult in ultra-thin SOI MOSFETs. The implementation of the front-gate split C-V method and its limitations for determining the front- and back-channel mobility are described. The mobility in the front channel is smaller than that in the back channel due to additional Coulomb scattering. We also discuss the 3D coupling effects that occur in FinFETs with triple-gate and omega-gate configurations. In low-doped or tall fins the corner effect is suppressed. Narrow devices are virtually immune to substrate effects due to a strong lateral coupling between the two lateral sides of the gate. Short-channel effects are drastically reduced when the lateral coupling screens the drain influence.
Źródło:: Journal of Telecommunications and Information Technology; 2007, 2; 14-24
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 4.

Tytuł:: Composition and electrical properties of ultra-thin SiOxNy layers formed by rf plasma nitrogen implantation/plasma oxidation processes
Autorzy:: Bieniek, T.
Beck, R. B.
Jakubowski, A.
Konarski, P.
Ćwil, M.
Hoffman, P.
Schmeißer, D.
Powiązania:: https://bibliotekanauki.pl/articles/308689.pdf
Data publikacji:: 2007
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: CMOS
gate stack
oxynitride
plasma implantation
Opis:: Experiments presented in this work are a summary of the study that examines the possibility of fabrication of oxynitride layers for Si structures by nitrogen implantation from rf plasma only or nitrogen implantation from rf plasma followed immediately by plasma oxidation process. The obtained layers were characterized by means of: ellipsometry, XPS and ULE-SIMS. The results of electrical characterization of NMOS Al-gate test structures fabricated with the investigated layers used as gate dielectric, are also discussed.
Źródło:: Journal of Telecommunications and Information Technology; 2007, 3; 9-15
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 5.

Tytuł:: Challenges in ultrathin oxide layers formation
Autorzy:: Beck, R.B.
Jakubowski, A.
Łukasiak, L.
Korwin-Pawłowski, M.
Powiązania:: https://bibliotekanauki.pl/articles/307646.pdf
Data publikacji:: 2001
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: silicon technology
oxidation
PECVD
RTO
gate oxide
ultrathin
layers
Opis:: In near future silicon technology cannot do without ultrathin oxides, as it becomes clear from the "Roadmap'2000". Formation, however, of such layers, creates a lot of technical and technological problems. The aim of this paper is to present the technological methods, that potentially can be used for formation of ultrathin oxide layers for next generations ICs. The methods are briefly described and their pros and cons are discussed.
Źródło:: Journal of Telecommunications and Information Technology; 2001, 1; 27-34
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 6.

Tytuł:: Ultrathin oxynitride films for CMOS technology
Autorzy:: Beck, R.B.
Jakubowski, A.
Powiązania:: https://bibliotekanauki.pl/articles/308025.pdf
Data publikacji:: 2004
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: MOS technology
gate stack
ultrathin oxynitride layers
high temperature processing
plasma processing
Opis:: In this work, a review of possible methods of oxynitride film formation will be given. These are different combinations of methods applying high-temperature oxidation and nitridation, as well as ion implantation and deposition techniques. The layers obtained using these methods differ, among other aspects in: nitrogen content, its profile across the ultrathin layer,... etc., which have considerable impact on device properties, such as leakage current, channel mobility, device stability and its reliability. Unlike high-temperature processes, which (understood as a single process step) usually do not allow the control of the nitrogen content at the silicon-oxynitride layer interface, different types of deposition techniques allow certain freedom in this respect. However, deposition techniques have been believed for many years not to be suitable for such a responsible task as the formation of gate dielectrics in MOS devices. Nowadays, this belief seems unjustified. On the contrary, these methods often allow the formation of the layers not only with a uniquely high content of nitrogen but also a very unusual nitrogen profile, both at exceptionally low temperatures. This advantage is invaluable in the times of tight restrictions imposed on the thermal budget (especially for high performance devices). Certain specific features of these methods also allow unique solutions in certain technologies (leading to simplifications of the manufacturing process and/or higher performance and reliability), such as dual gate technology for system-on-chip (SOC) manufacturing.
Źródło:: Journal of Telecommunications and Information Technology; 2004, 1; 62-69
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 7.

Tytuł:: Semiconductor cleaning technology for next generation material systems
Autorzy:: Ruzyllo, J.
Powiązania:: https://bibliotekanauki.pl/articles/308761.pdf
Data publikacji:: 2007
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: III-V compounds
FinFET
IC manufacturing
MEMS
MOS gate stack
semiconductor cleaning
Opis:: This paper gives a brief overview of the challenges wafer cleaning technology is facing in the light of advanced silicon technology moving in the direction of non-planar device structures and the need for modified cleans for semiconductors other than silicon. In the former case, the key issue is related to cleaning and conditioning of vertical surfaces in next generation CMOS gate structure as well as deep 3D geometries in MEMS devices. In the latter, an accelerated pace at which semiconductors other than silicon are being introduced into the mainstream manufacturing calls for the development of material specific wafer cleaning technologies. Examples of the problems related to each challenge are considered.
Źródło:: Journal of Telecommunications and Information Technology; 2007, 2; 44-48
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 8.

Tytuł:: SOI nanodevices and materials for CMOS ULSI
Autorzy:: Palestra, F.
Powiązania:: https://bibliotekanauki.pl/articles/308998.pdf
Data publikacji:: 2007
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: ballistic transport
gate misalignment
GIFBE
mobility enhancement
SOI
strain engineering
tunneling current
Opis:: A review of recently explored new effects in SOI nanodevices and materials is given. Recent advances in the understanding of the sensitivity of electron and hole transport to the tensile or compressive uniaxial and biaxial strains in thin film SOI are presented. The performance and physical mechanisms are also addressed in multi-gate Si, SiGe and Ge MOSFETs. The impact of gate misalignment or underlap, as well as the use of the back gate for charge storage in double-gate nanodevices and of capacitorless DRAMare also outlined.
Źródło:: Journal of Telecommunications and Information Technology; 2007, 2; 3-13
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 9.

Tytuł:: Evaluation of MOSFETs with crystalline high-k gate-dielectrics: device simulation and experimental data
Autorzy:: Zaunert, F.
Endres, R.
Stefanov, Y.
Schwalke, U.
Powiązania:: https://bibliotekanauki.pl/articles/308785.pdf
Data publikacji:: 2007
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: crystalline high-k gate dielectric
rare-earth oxide
praseodymium oxide
gadolinium oxide
damascene metal gate
CMP
CMOS process
TSUPREM4
MEDICI
interface state density
carrier mobility
remote coulomb scattering
Opis:: The evaluation of the world's first MOSFETs with epitaxially-grown rare-earth high-k gate dielectrics is the main issue of this work. Electrical device characterization has been performed on MOSFETs with high-k gate oxides as well as their reference counterparts with silicon dioxide gate dielectric. In addition, by means of technology simulation with TSUPREM4, models of these devices are established. Current-voltage characteristics and parameter extraction on the simulated structures is conducted with the device simulator MEDICI. Measured and simulated device characteristics are presented and the impact of interface state and fixed charge densities is discussed. Device parameters of high-k devices fabricated with standard poly-silicon gate and replacement metal gate process are compared.
Źródło:: Journal of Telecommunications and Information Technology; 2007, 2; 78-85
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 10.

Tytuł:: Challenges for 10 nm MOSFET process integration
Autorzy:: Östling, M.
Malm, B. G.
Haartman, M.
Hallstedt, J.
Zhang, Z.
Hellström, P. E.
Zhang, S.
Powiązania:: https://bibliotekanauki.pl/articles/309004.pdf
Data publikacji:: 2007
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Tematy:: sstrained silicon
silicon-germanium
silicon-on-insulator (SOI)
high-k dielectrics
hafnium oxide
nanowire
low frequency noise
mobility
metal gate
Opis:: An overview of critical integration issues for future generation MOSFETs towards 10 nm gate length is presented. Novel materials and innovative structures are discussed. The need for high-k gate dielectrics and a metal gate electrode is discussed. Different techniques for strain-enhanced mobility are discussed. As an example, ultra thin body SOI devices with high mobility SiGe channels are demonstrated.
Źródło:: Journal of Telecommunications and Information Technology; 2007, 2; 25-32
1509-4553
1899-8852
Pojawia się w:: Journal of Telecommunications and Information Technology
Dostawca treści:: Biblioteka Nauki

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