Informacja

Drogi użytkowniku, aplikacja do prawidłowego działania wymaga obsługi JavaScript. Proszę włącz obsługę JavaScript w Twojej przeglądarce.

English (EN)·Polski (PL)·Yкраїнський (UK)
Przejdź do strony domowej biblioteki Centralna Biblioteka Wojskowa Link otwiera się w nowym oknie Logo biblioteki Prolib Integro - strona głównaCentralna Biblioteka Wojskowa

Wyszukujesz frazę "CMOS" wg kryterium: Temat

  Lista filtrów
Wyrównaj
    Wyświetlanie 1-14 z 14
    Tytuł:
    Ultra-low-voltage LNA with high gain and low noise figure
    Autorzy:
    Bastos, I.
    Oliveira, L. B.
    Oliveira, J. P.
    Goes, J.
    Silva, M. M.
    Powiązania:
    https://bibliotekanauki.pl/articles/397785.pdf
    Data publikacji:
    2013
    Wydawca:
    Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
    Tematy:
    LNA
    CMOS
    noise cancellation
    redukcja szumów
    Opis:
    We present a balun LNA with noise and distortion cancellation using double feedforward. A common-gate and a common-source stage are combined, and their resistive loads are replaced by transistors biased close to saturation to allows low supply voltage, without gain degradation. The proposed feedforward boosts the LNA gain and reduces the noise figure (NF). Simulation results with a 130 nm CMOS technology show that the gain is up to 24 dB and the NF is below 3.2 dB. The total power dissipation is 2.25 mW, leading to an FoM of 6.4 mW-1 with 0.6 V supply.
    Źródło:
    International Journal of Microelectronics and Computer Science; 2013, 4, 3; 124-128
    2080-8755
    2353-9607
    Pojawia się w:
    International Journal of Microelectronics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Versatile low-output-resistance low-voltage current-to-voltage analog converter
    Autorzy:
    Wojtyna, R.
    Powiązania:
    https://bibliotekanauki.pl/articles/397867.pdf
    Data publikacji:
    2016
    Wydawca:
    Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
    Tematy:
    CMOS analog integrated circuits
    low-voltage signal processing
    current to voltage conversion
    transresistor
    układy analogowe CMOS
    układy scalone CMOS
    przetwarzanie sygnałów
    konwersja prąd na napięcie
    transrezystor
    Opis:
    The paper presents a simple low-voltage transresistor attractive for on-chip analog-signal-processing. The proposed circuit offers not only an almost rail-to-rail operation and quite good linearity of DC transfer characteristic but also reasonably low value of its output resistance. This enables a voltage mode operation even if the transresistor is loaded by a not necessarily very high loading resistance. The obtained result is due to adding to the transresistor-input-stage a simple rail-to-rail voltage follower. The presented solution is an original proposal of the author. Input stage of the transresistor is built of only 4 MOS transistors and creates a simple quasi-linear current-to-voltage convertor. Output stage of it is built of 9 MOS transistors, plays a role of a very precise atypical voltage follower. In respect of simplicity and headroom, the proposed follower is better than conventional OA-based voltage followers. Preliminary simulation results are in a good agreement with the theory presented.
    Źródło:
    International Journal of Microelectronics and Computer Science; 2016, 7, 2; 73-78
    2080-8755
    2353-9607
    Pojawia się w:
    International Journal of Microelectronics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Cascode amplifiers with low-gain variability and gain enhancement using a body-biasing technique
    Autorzy:
    Pereira, N
    Oliveira, L. B.
    Goes, J.
    Oliveira, J. P.
    Powiązania:
    https://bibliotekanauki.pl/articles/398063.pdf
    Data publikacji:
    2013
    Wydawca:
    Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
    Tematy:
    amplifier
    body-biasing
    cascode
    CMOS analog circuits
    PVT compensation
    wzmacniacz
    kaskoda
    układy analogowe CMOS
    kompensacja PVT
    Opis:
    This paper presents a simple circuit technique to reduce gain variability with PVT variations in cascode amplifiers using a body-biasing scheme, while enhancing the overall gain of the amplifier. Simulation results of a standard telescopic-cascode amplifier, in two different nanoscale CMOS technologies (130 nm and 65 nm) show that the proposed compensated circuit amplifier exhibits a (DC) gain variability smaller (below ± 0.5 dB) than the original (uncompensated) circuit, while reaching a gain enhancement of about 3 dB. The required auxiliary biasing circuit dissipates around 5% of the main amplifier circuit.
    Źródło:
    International Journal of Microelectronics and Computer Science; 2013, 4, 3; 98-102
    2080-8755
    2353-9607
    Pojawia się w:
    International Journal of Microelectronics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Power-saving voltage-to-current conversion with the use of CMOS differential amplifier
    Autorzy:
    Wojtyna, R.
    Powiązania:
    https://bibliotekanauki.pl/articles/398104.pdf
    Data publikacji:
    2015
    Wydawca:
    Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
    Tematy:
    analog signal processing
    differential amplifier
    CMOS electronics
    low-power analog circuits
    analogowe przetwarzanie sygnałów
    wzmacniacz różnicowy
    CMOS
    obwody niskiego napięcia
    Opis:
    Differential amplifiers are well known as input stage preamplifiers. This is because they exhibit the ability to reduce unwanted common-mode effects considerably. As a consequence, both noise and input signal of the amplifier can have low values. Proper operation of differential amplifiers is possible when implemented in chip form. For typical use of such CMOS amplifiers, input signals are delivered to differential-pair gate-terminals while tail terminal is used to ensure the required bias of the pair. The paper shows that the roles of gates and tail terminal can be changed. In other words, the tail current can be used as input signal while the gate ones as voltages controlling the amplifier gain. This enables to combine the achievable low noise with power efficient operation of the circuit. Necessary conditions for that are discussed in this paper. Suitability of atypically used differential amplifiers for voltage-to-current conversion is explained. Two examples of CMOS circuits implementing power economic conversion of this type are presented.
    Źródło:
    International Journal of Microelectronics and Computer Science; 2015, 6, 3; 96-101
    2080-8755
    2353-9607
    Pojawia się w:
    International Journal of Microelectronics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Design of a novel cascoded CMOS OpAmp with high gain and ± 1.5 V power supply voltage
    Autorzy:
    Lipka, B
    Kleine, U.
    Scheytt, J. -C.
    Schmalz, K.
    Powiązania:
    https://bibliotekanauki.pl/articles/397853.pdf
    Data publikacji:
    2010
    Wydawca:
    Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
    Tematy:
    niskie napięcie
    CMOS wzmacniacz operacyjny
    stopień kaskodowy
    zagnieżdżona kompensacja Millera
    low voltage
    CMOS operational amplifier
    cascoded stage
    nested Miller compensation
    Opis:
    The design of a novel CMOS operational amplifier with two differential input stages is described. Prototype circuits have been fabricated and measured successfully. By using a nested Miller compensation the stability of the operational amplifier is ensured. The layout has been created automatically by using the ALADIN tool [6-9]. The small signal model for the amplifier is depicted and the test results are presented.
    Źródło:
    International Journal of Microelectronics and Computer Science; 2010, 1, 1; 15-18
    2080-8755
    2353-9607
    Pojawia się w:
    International Journal of Microelectronics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    A MOSFET only, step-up DC DC micro power converter, for solar energy harvesting applications
    Autorzy:
    Carvalho, C.
    Paulino, N.
    Powiązania:
    https://bibliotekanauki.pl/articles/398057.pdf
    Data publikacji:
    2010
    Wydawca:
    Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
    Tematy:
    układy CMOS
    elektronika
    energia zbiorów
    układy zarządzania energią
    komórki fotowoltaiczne
    CMOS circuits
    electronics
    energy harvesting
    power management circuits
    PV cells
    Opis:
    In this paper, a step-up micro power converter for solar energy harvesting applications is presented. The circuit is based on a switched-capacitor voltage doubler architecture with MOSFET capacitors, which results in an area approximately eight times smaller than using MiM capacitors for the 0.13 žm CMOS technology. In order to compensate for the loss of efficiency, due to the larger parasitic capacitances, a charge reutilization scheme is employed. The circuit uses a phase controller, designed specifically to work with the series of two PV cells, in order to regulate the output voltage to 1.2 V. Electrical simulations of the circuit, together with an equivalent electrical model of a PV cell, show that the circuit can deliver a power of 536.1 žW to the load, while drawing a power of 799.8 žW from two PV cells stacked in series, corresponding to a maximum efficiency of 67%.
    Źródło:
    International Journal of Microelectronics and Computer Science; 2010, 1, 2; 112-119
    2080-8755
    2353-9607
    Pojawia się w:
    International Journal of Microelectronics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Upgraded low voltage analog Current-to-Voltage converter with negative feedback
    Autorzy:
    Wojtyna, R.
    Powiązania:
    https://bibliotekanauki.pl/articles/397781.pdf
    Data publikacji:
    2017
    Wydawca:
    Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
    Tematy:
    analog signal processing
    current-to-voltage converters
    feedback theory
    analog CMOS electronics
    analogowe przetwarzanie sygnałów
    przetworniki prądowo-napięciowe
    teoria sprzężenia zwrotnego
    CMOS
    Opis:
    In this paper, an improved version of a current to voltage (C-V) converter is proposed. As compared to the previous version, the number of used transistors has been reduced by 1 and equals 7. The main results of this change are: an improvement of the circuit transfer function linearity, reduction the converter input resistance and decrease of the required supply voltage. Improvements in the considered converter results not only from the reduction of the number of the used transistors but also from the proposed realization of the feedback loop. In this way, it was possibly to get a strong loop gain. As a results, the achieved minimum supply voltage has been reduces from 2V, in case of the previous published converter version, to as low level as 1.2 V, in the case of the newly proposed solution. As for the linearity of the C-V transfer function, apart from its strong loop gain, an important role play also output transistors operating in a small drain to source region (linear region). Working in this region, one obtains a quasi linear voltage to current relationship. The theoretical and simulation results are in a good agreement and are promising.
    Źródło:
    International Journal of Microelectronics and Computer Science; 2017, 8, 2; 80-84
    2080-8755
    2353-9607
    Pojawia się w:
    International Journal of Microelectronics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Analysis and design of CMOS coupled multivibrators
    Autorzy:
    Casaleiro, J.
    Lopes, H. F.
    Oliveira, L. B.
    Filanovsky, I.
    Powiązania:
    https://bibliotekanauki.pl/articles/397859.pdf
    Data publikacji:
    2010
    Wydawca:
    Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
    Tematy:
    multiwibrator
    CMOS oscillator
    multivibrator
    quadrature outputs
    van der Pol oscillator
    WMTS appications
    Opis:
    In this paper a wideband MOS quadrature oscillator constituted by two multivibrators is presented. Two different forms of coupling, named here as soft and hard, are investigated. Simulations are performed in a 0.13 žm CMOS technology to obtain the tuning range, the synchronization transients, and the influence of mismatches in timing capacitors and charging currents on synchronization. It is found that hard coupling reduces the quadrature error (about 1°, with 5% mismatches in timing capacitors and charging currents) and results in a low phase-noise (about 2 dB improvement) with respect to soft coupling. Either a single multivibrator or coupled multivibrators can be locked to an external synchronizing harmonic frequency, and the locking range is investigated by simulations. The simulations are done for oscillators covering the WTMS frequency bands.
    Źródło:
    International Journal of Microelectronics and Computer Science; 2010, 1, 3; 249-256
    2080-8755
    2353-9607
    Pojawia się w:
    International Journal of Microelectronics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Improvements of high-voltage trapezoidal waveform edge-rounding circuit
    Autorzy:
    Jankowski, Mariusz
    Powiązania:
    https://bibliotekanauki.pl/articles/397803.pdf
    Data publikacji:
    2018
    Wydawca:
    Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
    Tematy:
    CMOS integrated circuits
    high-voltage techniques
    wireless communications
    current-mode circuits
    RFID tag
    harmonic distortion
    electromagnetic compatibility
    układy scalone CMOS
    techniki wysokonapięciowe
    komunikacja bezprzewodowa
    obwód prądowy
    zniekształcenie harmoniczne
    kompatybilność elektromagnetyczna
    Opis:
    This paper introduces a solution to a design problem caused by necessity of electromagnetic noise reduction in simple close-range wireless command and control systems, including Radio-frequency identification (RFID) systems. Trade-off between simplicity of data transmission, detection and decoding on one side vs. presence of high frequency harmonics in transmitted signals on the other makes some designers choose approach in which trapezoidal waveforms are used instead of rectangular ones. Moreover, edges of trapezoidal waveforms are additionally rounded to further limit presence of higher harmonics and thus to comply to EMI regulations and requirements. The paper proposes a solution based on a reimplementation of a high-voltage structure already proposed by the author, but implemented with use of different semiconductor technology process. Utilization of this new process and devices available in this technology makes possible significant increase of the circuit operation quality.
    Źródło:
    International Journal of Microelectronics and Computer Science; 2018, 9, 3; 93-100
    2080-8755
    2353-9607
    Pojawia się w:
    International Journal of Microelectronics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Analysis and design of a MOSFET-only wideband balun LNA
    Autorzy:
    Bastos, I.
    Oliveira, L. B.
    Goes, J.
    Silva, M.
    Powiązania:
    https://bibliotekanauki.pl/articles/397861.pdf
    Data publikacji:
    2010
    Wydawca:
    Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
    Tematy:
    tranzystor polowy MOS-tylko obwody
    redukcja hałasu
    CMOS LNAs
    MOSFET-only circuits
    noise cancelling
    wideband LNA
    Opis:
    In this paper we present a MOSFET-only implementation of a balun LNA. This LNA is based on the combination of a common-gate and a common-source stage with cancellation of the noise of the common-gate stage. In this circuit, we replace resistors by transistors, to reduce area and cost, and to minimize the effect of process and supply variations and mismatches. In addition, we obtain a higher gain for the same voltage drop. Thus, the LNA gain is optimized and the noise figure (NF) is reduced. We derive equations for the gain, input matching and NF. The performance of this new topology is compared with that of a conventional LNA with resistors. Simulation results with a 130 nm CMOS technology show that we obtain a balun LNA with a peak gain of 20.2 dB (about 2 dB improvement), and a spot NF lower than 2.4 dB. The total power consumption is only 4.8 mW for a bandwidth higher than 6 GHz.
    Źródło:
    International Journal of Microelectronics and Computer Science; 2010, 1, 3; 241-248
    2080-8755
    2353-9607
    Pojawia się w:
    International Journal of Microelectronics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Co-design of a low-power RF receiver and piezoelectric energy harvesting power supply for a Wireless Sensor Node
    Autorzy:
    Mancelos, N
    Correia, J
    Oliveira, J. P.
    Oliveira, L. B.
    Powiązania:
    https://bibliotekanauki.pl/articles/398018.pdf
    Data publikacji:
    2014
    Wydawca:
    Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
    Tematy:
    CMOS RF analog front-end
    low-voltage wideband balun LNA
    passive mixer
    piezoelectric energy harvesting
    active full bridge rectifier
    LDO regulator
    układ analogowy CMOS
    balun szerokopasmowy
    mikser pasywny
    energia piezoelektryczna
    prostownik aktywny
    prostownik mostkowy
    regulator LDO
    Opis:
    A low-voltage RF CMOS receiver front-end and an energy harvesting power circuit for a piezoelectric source are presented as a co-designed solution for a Wireless Sensor Node. A MOSFET-only Wideband balun LNA with noise cancelling and a 0.6 V supply voltage is designed in conjunction with a passive mixer. The passive mixer operates in current mode, allowing a minimal introduction of voltage noise and a good linearity. The receiver front-end reaches a total voltage conversion gain of 31 dB, a 0.1-5.2 GHZ bandwidth, an IIP3 value of -1.35 dBm, and a noise figure inferior to 9 dB. The total power consumption is 1.95 mW. The energy harvesting power circuit consists of an active full bridge cross-coupled rectifier followed by a low-dropout (LDO) regulator, and it is able to guarantee a power output of 6 mW with a regulated output voltage of 0.6 V, for typical vibration patterns.
    Źródło:
    International Journal of Microelectronics and Computer Science; 2014, 5, 4; 136-143
    2080-8755
    2353-9607
    Pojawia się w:
    International Journal of Microelectronics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    A 65 nm CMOS Resistorless Current Reference Source with Low Sensitivity to PVT Variations
    Autorzy:
    Łukaszewicz, M.
    Borejko, T.
    Pleskacz, W. A.
    Powiązania:
    https://bibliotekanauki.pl/articles/397920.pdf
    Data publikacji:
    2012
    Wydawca:
    Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
    Tematy:
    efekt objętościowy
    obwody zasilające
    napięcie progowe
    current reference
    65 nm CMOS
    body effect
    power supply circuits
    threshold voltage
    Opis:
    This paper describes a resistorless current reference source, e.g. for fast communication interfaces. Addition of currents with opposite temperature coefficient (PTC and NTC) and body effect have been used to temperature compensation. Cascode structures have been used to improve the power supply rejection ratio. The reference current source has been designed in a GLOBALFOUNDRIES 65 nm technology. The presented circuit achieves 59 ppm/°C temperature coefficient over range of -40°C to 125°C. Reference current susceptibility to process parameters variation is ± 2.88%. The power supply rejection ratio without any filtering capacitor at 100 Hz and 10 MHz is lower than -142 dB and -131 dB, respectively.
    Źródło:
    International Journal of Microelectronics and Computer Science; 2012, 3, 4; 119-124
    2080-8755
    2353-9607
    Pojawia się w:
    International Journal of Microelectronics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    On-chip current-mode approach to thwart CPA attacks in CMOS nanometer technology
    Autorzy:
    Bellizia, D.
    Scotti, G.
    Trifiletti, A.
    Powiązania:
    https://bibliotekanauki.pl/articles/398086.pdf
    Data publikacji:
    2016
    Wydawca:
    Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
    Tematy:
    IoT
    internet of things (IoT)
    Power Analysis Attacks
    smart card
    CPA
    current-mode
    Side Channel Analysis
    CMOS
    Cryptography
    PRESENT
    Internet rzeczy
    karta inteligentna
    moduły prądowe
    kryptografia
    Opis:
    The protection of information that reside in smart devices like IoT nodes is becoming one of the main concern in modern design. The possibility to mount a non-invasive attack with no expensive equipment, such as a Power Analysis Attack (PAA), remarks the needs of countermeasures that aims to thwart attacks exploiting power consumption. In addition to that, designers have to deal with demanding requirements, since those smart devices require stringent area and energy constraints. In this work, a novel analog-level approach to counteract PAA is presented, taking benefits of the current-mode approach. The kernel of this approach is that the information leakage exploited in a PAA is leaked through current absorption of a cryptographic device. Thanks to an on-chip measuring of the current absorbed by the cryptographic logic, it is possible to generate an error signal. Throughout a current-mode feedback mechanism, the data-dependent component of the overall consumption can be compensated, making the energy requirement constant at any cycle and thwarting the possibility to recover sensible information. Two possible implementations of the proposed approach are presented in this work and their effectiveness has been evaluated using a 40nm CMOS design library. The proposed approach is able to increase the Measurements to Disclosure (MTD) of at least three orders of magnitude, comparing to the unprotected implementation. It has to be pointed out that the on-chip current-mode suppressor, based on the proposed approach, is able to provide a very good security performance, while requiring a very small overhead in terms of silicon area (xl.007) and power consumption (xl.07).
    Źródło:
    International Journal of Microelectronics and Computer Science; 2016, 7, 4; 147-156
    2080-8755
    2353-9607
    Pojawia się w:
    International Journal of Microelectronics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Analysis of a Simple Method of CMOS IC Design for Yield Optimization
    Autorzy:
    Tomaszewski, D.
    Yakupov, M.
    Powiązania:
    https://bibliotekanauki.pl/articles/397989.pdf
    Data publikacji:
    2012
    Wydawca:
    Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
    Tematy:
    CMOS
    projektowanie pod kątem zysku
    funkcja gęstości prawdopodobieństwa
    dystrybuanta
    modelowanie statystyczne
    BPV
    symulacja SPICE
    design centering
    design for yield
    probability density function
    cumulative distribution function
    statistical modeling
    BPV method
    SPICE simulation
    Opis:
    A simple approach for CMOS integrated circuit (IC) design taking into account a process variability and oriented towards optimization of a parametric yield has been presented. Its concept is based on cumulative distribution functions of random variables representing IC performances subject to process variations. In the method it has been assumed that CMOS process statistical data are expressed in terms of so-called process parameter distributions. Thus the design centering is done via layout parameter tuning. The approach relies on maximizing the probability that random variables corresponding to IC performances remain within the performance boundaries. Also, a methodology for statistical characterization of CMOS process has been briefly described. Finally, the method operation has been illustrated using analytical and SPICE models of CMOS inverter, operational amplifier and ring oscillator.
    Źródło:
    International Journal of Microelectronics and Computer Science; 2012, 3, 3; 81-87
    2080-8755
    2353-9607
    Pojawia się w:
    International Journal of Microelectronics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-14 z 14

      Ta witryna wykorzystuje pliki cookies do przechowywania informacji na Twoim komputerze. Pliki cookies stosujemy w celu świadczenia usług na najwyższym poziomie, w tym w sposób dostosowany do indywidualnych potrzeb. Korzystanie z witryny bez zmiany ustawień dotyczących cookies oznacza, że będą one zamieszczane w Twoim komputerze. W każdym momencie możesz dokonać zmiany ustawień dotyczących cookies