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    Wyświetlanie 1-3 z 3
    Tytuł:
    A low-jitter, full-differential PLL in 0.18μm CMOS technology
    Autorzy:
    Modarresi, F.
    Ghasemzadeh, M.
    Mazlumi, M.
    Amini, A.
    Abolfathi, T.
    Powiązania:
    https://bibliotekanauki.pl/articles/397765.pdf
    Data publikacji:
    2016
    Wydawca:
    Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
    Tematy:
    full differential PLL
    PFD
    VCO
    low jitter
    CPL
    pętla synchronizacji fazy
    PLL
    generator sterowany napięciem
    niski jitter
    Opis:
    This paper presents a Phase Locked Loop (PLL) which works with minimum jitter in the operation frequency range of 600MHZ to 900MHZ. Utilizing a full differential architecture that consists of several blocks of differential VCO, a differential PFD and a differential CPL leads to limiting the RMS jitter to 4.06ps, with 50mV power supply noise in the frequency range of 750MHz. Simulation results using 0.18μm CMOS TSMC standard technology demonstrate the power-consumption of 4.6mW at the supply voltage of 1.8V.
    Źródło:
    International Journal of Microelectronics and Computer Science; 2016, 7, 4; 119-122
    2080-8755
    2353-9607
    Pojawia się w:
    International Journal of Microelectronics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Analysis and optimization of LUDMOS transistors on a 0.18um SOI CMOS technology
    Autorzy:
    Toulon, G.
    Cortés, I.
    Morancho, F.
    Villard, B.
    Powiązania:
    https://bibliotekanauki.pl/articles/397849.pdf
    Data publikacji:
    2010
    Wydawca:
    Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
    Tematy:
    moc MOSFET
    LDMOS
    RESURF
    STI (płytki rów izolacyjny)
    krzem na izolatorze
    power MOSFET
    STI (shallow trench isolation)
    superjunction
    silicon-on-insulator
    Opis:
    This paper is focused on the design and optimization of power LDMOS transistors (V br > 120 Volts) with the purpose of being integrated in a new generation of Smart Power technology based upon a 0.18 μm SOI-CMOS technology. The benefits of applying the shallow trench isolation (STI) concept along with the 3D RESURF concept in the LDMOS drift region is analyzed in terms of the main static (Ron-sp/Vbr tradeoff) and dynamic (Miller capacitance and QgxRon FOM) characteristics. The influence of some design parameters such as the polysilicon gate electrode length and the STI length are exhaustively analyzed.
    Źródło:
    International Journal of Microelectronics and Computer Science; 2010, 1, 1; 3-8
    2080-8755
    2353-9607
    Pojawia się w:
    International Journal of Microelectronics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    On-chip current-mode approach to thwart CPA attacks in CMOS nanometer technology
    Autorzy:
    Bellizia, D.
    Scotti, G.
    Trifiletti, A.
    Powiązania:
    https://bibliotekanauki.pl/articles/398086.pdf
    Data publikacji:
    2016
    Wydawca:
    Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
    Tematy:
    IoT
    internet of things (IoT)
    Power Analysis Attacks
    smart card
    CPA
    current-mode
    Side Channel Analysis
    CMOS
    Cryptography
    PRESENT
    Internet rzeczy
    karta inteligentna
    moduły prądowe
    kryptografia
    Opis:
    The protection of information that reside in smart devices like IoT nodes is becoming one of the main concern in modern design. The possibility to mount a non-invasive attack with no expensive equipment, such as a Power Analysis Attack (PAA), remarks the needs of countermeasures that aims to thwart attacks exploiting power consumption. In addition to that, designers have to deal with demanding requirements, since those smart devices require stringent area and energy constraints. In this work, a novel analog-level approach to counteract PAA is presented, taking benefits of the current-mode approach. The kernel of this approach is that the information leakage exploited in a PAA is leaked through current absorption of a cryptographic device. Thanks to an on-chip measuring of the current absorbed by the cryptographic logic, it is possible to generate an error signal. Throughout a current-mode feedback mechanism, the data-dependent component of the overall consumption can be compensated, making the energy requirement constant at any cycle and thwarting the possibility to recover sensible information. Two possible implementations of the proposed approach are presented in this work and their effectiveness has been evaluated using a 40nm CMOS design library. The proposed approach is able to increase the Measurements to Disclosure (MTD) of at least three orders of magnitude, comparing to the unprotected implementation. It has to be pointed out that the on-chip current-mode suppressor, based on the proposed approach, is able to provide a very good security performance, while requiring a very small overhead in terms of silicon area (xl.007) and power consumption (xl.07).
    Źródło:
    International Journal of Microelectronics and Computer Science; 2016, 7, 4; 147-156
    2080-8755
    2353-9607
    Pojawia się w:
    International Journal of Microelectronics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-3 z 3

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