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Wyszukujesz frazę "parallel computation" wg kryterium: Temat


Wyświetlanie 1-2 z 2
Tytuł:
Parallel Computation Approaches to Optimize Learning Systems
Autorzy:
Czyż, T.
Rudek, R.
Selvaraj, H.
Powiązania:
https://bibliotekanauki.pl/articles/226487.pdf
Data publikacji:
2011
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
parallel computation
metaheuristic
scheduling
learning
Opis:
This paper is devoted to the total tardiness minimization scheduling problem, where the efficiency of a processor increases due to its learning. Such problems model real-life settings that occur in the presence of a human learning (industry, manufacturing, management) and in some computer systems. However, the increasing growth of significant achievements in the field of artificial intelligence and machine learning is a premise that the human-like learning will be present in mechanized industrial processes that are controlled or performed by machines as well as in the greater number of multi-agent computer systems. Therefore, the optimization algorithms dedicated in this paper for scheduling problems with learning are not only the answer for present day scheduling problems (where human plays important role), but they are also a step forward to the improvement of self-learning and adapting systems that undeniably will occur in a new future. To solve the analysed problem, we propose parallel computation approaches that are based on NEH, tabu search and simulated annealing algorithms. The numerical analysis confirm high accuracy of these methods and show that the presented approaches significantly decrease running times of simulated annealing and tabu search and also reduce the running times of NEH.
Źródło:
International Journal of Electronics and Telecommunications; 2011, 57, 2; 223-228
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
DC Large-Scale Simulation of Nonlinear Circuits on Parallel Processors
Autorzy:
Udave, D. E. C.
Ogrodzki, J.
de Anda, G. M. A.
Powiązania:
https://bibliotekanauki.pl/articles/226087.pdf
Data publikacji:
2012
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
circuit simulation
parallel computation
DC analysis
circuit decomposition
Opis:
Newton-Raphson DC analysis of large-scale nonlinear circuits may be an extremely time consuming process even if sparse matrix techniques and bypassing of nonlinear models calculation are used. A slight decrease in the time required for this task may be enabled on multi-core, multithread computers if the calculation of the mathematical models for the nonlinear elements as well as the stamp management of the sparse matrix entries is managed through concurrent processes. In this paper it is shown how the numerical complexity of this problem (and thus its solution time) can be further reduced via the circuit decomposition and parallel solution of blocks taking as a departure point the Bordered-Block Diagonal (BBD) matrix structure. This BBD-parallel approach may give a considerable profit though it is strongly dependent on the system topology. This paper presents a theoretical foundation of the algorithm, its implementation, and numerical complexity analysis in virtue of practical measurements of matrix operations.
Źródło:
International Journal of Electronics and Telecommunications; 2012, 58, 3; 285-295
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
    Wyświetlanie 1-2 z 2

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