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    Wyświetlanie 1-12 z 12
    Tytuł:
    A - 5 dBm 400MHz OOK Transmitter for Wireless Medical Application
    Autorzy:
    Yousefi, M.
    Koozehkanani, Z. D.
    Jangi, H.
    Nasirzadeh, N.
    Sobhi, J.
    Powiązania:
    https://bibliotekanauki.pl/articles/226054.pdf
    Data publikacji:
    2014
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    transmitter
    power amplifier
    on-off keying
    low power
    Opis:
    A 400 MHz high efficiency transmitter for wireless medical application is presented in this paper. Transmitter architecture with high-energy efficiencies is proposed to achieve high data rate with low power consumption. In the on-off keying transmitters, the oscillator and power amplifier are turned off when the transmitter sends 0 data. The proposed class-e power amplifier has high efficiency for low level output power. The proposed on-off keying transmitter consumes 1.52 mw at-5 dBm output by 40 Mbps data rate and energy consumption 38 pJ/bit. The proposed transmitter has been designed in 0.18μm CMOS technology.
    Źródło:
    International Journal of Electronics and Telecommunications; 2014, 60, 2; 193-198
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Design of Low–power 4-bit Flash ADC Using Multiplexer Based Encoder in 90nm CMOS Process
    Autorzy:
    Shylu Sam, D. S.
    Sam Paul, P.
    Jeba Jingle, Diana
    Mano Paul, P.
    Samuel, Judith
    Reshma, J.
    Sudeepa, P. Sarah
    Evangeline, G.
    Powiązania:
    https://bibliotekanauki.pl/articles/2124770.pdf
    Data publikacji:
    2022
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    flash ADC
    low power
    dynamic comparator
    encoder
    Opis:
    This work describes a 4-bit Flash ADC with low power consumption. The performance metrics of a Flash ADC depend on the kind of comparator and encoder used. Hence openloop comparator and mux-based encoder are used to obtain improved performance. Simulation results show that the simulated design consumes 0.265mW of power in 90nm CMOS technology using cadence-virtuoso software. The circuit operates with an operating frequency of 100MHz and a supply voltage of 1V.
    Źródło:
    International Journal of Electronics and Telecommunications; 2022, 68, 3; 565--570
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    A Modified Signal Feed-Through Pulsed Flip-Flop for Low Power Applications
    Autorzy:
    Panahifar, E.
    Hassanzadeh, A.
    Powiązania:
    https://bibliotekanauki.pl/articles/226160.pdf
    Data publikacji:
    2017
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    low power
    pulsed flip-flop
    delay
    leakage power
    dynamic power
    Opis:
    In this paper a modified signal feed-through pulsed flip-flop has been presented for low power applications. Signal feed-through flip-flop uses a pass transistor to feed input data directly to the output. Feed through transistor and feedback signals have been modified for delay, static and dynamic power reduction. HSPICE simulation shows 22% reduction in leakage power and 8% of dynamic power. Delay has been reduced by 14% using TSMC 90nm technology parameters. The proposed pulsed flip-flop has the lowest PDP (Power Delay Product) among other pulsed flip-flops discussed.
    Źródło:
    International Journal of Electronics and Telecommunications; 2017, 63, 3; 241-246
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Design and Noise Analysis of a Novel Auto-Zeroing Structure for Continuous-Time Instrumentation Amplifiers
    Autorzy:
    Maréchal, S.
    Nys, O.
    Krummenacher, F.
    Chevroulet, M.
    Kayal, M.
    Powiązania:
    https://bibliotekanauki.pl/articles/226106.pdf
    Data publikacji:
    2013
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    front-end
    instrumentation amplifier
    low-noise
    low power
    chopper
    auto-zero
    Opis:
    This paper introduces a low-noise, low-power amplifier for high-impedance sensors. An innovative circuit using an auto-zeroed architecture combined with frequency modulation to reject offset and low-frequency noise is proposed and analysed. Special care was given to avoid broadband noise aliasing and chopping in the signal path, and to minimize both the resulting equivalent input offset voltage and equivalent input biasing current. The theoretical noise analysis of the proposed topology covers most of the noise sources of the circuit. Simulations show that the input-referred noise level of the circuit is 13.4nV/√Hz for a power consumption of 85µA with a power supply from 1.8V to 3.6V.
    Źródło:
    International Journal of Electronics and Telecommunications; 2013, 59, 4; 397-404
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Low-Power High-Speed Double Gate 1-bit Full Adder Cell
    Autorzy:
    Kumar, R.
    Roy, S.
    Bhunia, C. T.
    Powiązania:
    https://bibliotekanauki.pl/articles/226653.pdf
    Data publikacji:
    2016
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    low-power full-adder
    low-power CMOS design
    multiplexer based full-adder design
    multi-threshold voltage based full-adder design
    pass transmission logic
    Opis:
    In this paper, we proposed an efficient full adder circuit using 16 transistors. The proposed high-speed adder circuit is able to operate at very low voltage and maintain the proper output voltage swing and also balance the power consumption and speed. Proposed design is based on CMOS mixed threshold voltage logic (MTVL) and implemented in 180nm CMOS technology. In the proposed technique the most time-consuming and power consuming XOR gates and multiplexer are designed using MTVL scheme. The maximum average power consumed by the proposed circuit is 6.94μW at 1.8V supply voltage and frequency of 500 MHz, which is less than other conventional methods. Power, delay, and area are optimized by using pass transistor logic and verified using the SPICE simulation tool at desired broad frequency range. It is also observed that the proposed design may be successfully utilized in many cases, especially whenever the lowest power consumption and delay are aimed.
    Źródło:
    International Journal of Electronics and Telecommunications; 2016, 62, 4; 329-334
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Graphene-based Current Mode Logic Circuits : a Simulation Study for an Emerging Technology
    Autorzy:
    Abdollahi, Hassan
    Hooshmand, Reza
    Owlia, Hadi
    Powiązania:
    https://bibliotekanauki.pl/articles/226818.pdf
    Data publikacji:
    2019
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    current mode logic (CML)
    graphene
    graphene FET
    low-power design
    Opis:
    In this paper, the usage of graphene transistors is introduced to be a suitable solution for extending low power designs. Static and current mode logic (CML) styles on both nanoscale graphene and silicon FINFET technologies are compared. Results show that power in CML styles approximately are independent of frequency and the graphene-based CML (G-CML) designs are more power-efficient as the frequency and complexity increase. Compared to silicon-based CML (Si-CML) standard cells, there is 94% reduction in power consumption for G-CML counterparts. Furthermore, a G-CML 4-bit adder respectively offers 8.9 and 1.7 times less power and delay than the Si-CML adder.
    Źródło:
    International Journal of Electronics and Telecommunications; 2019, 65, 3; 381-388
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Double-gate MOSFET Model Implemented in Verilog-AMS Language for the Transient Simulation and the Configuration of Ultra Low-power Analog Circuits
    Autorzy:
    Smaani, Billel
    Meraihi, Yacin
    Nafa, Fares
    Benlatreche, Mohamed Salah
    Akroum, Hamza
    Latreche, Saida
    Powiązania:
    https://bibliotekanauki.pl/articles/2055208.pdf
    Data publikacji:
    2021
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    double-gate MOSFET
    compact model
    ultra low power analog circuits
    Opis:
    This paper deals with the implementation of a DC and AC double-gate MOSFET compact model in the Verilog-AMS language for the transient simulation and the configuration of ultra low-power analog circuits. The Verilog-AMS description of the proposed model is inserted in SMASH circuit simulator for the transient simulation and the configuration of the Colpitts oscillator, the common-source amplifier, and the inverter. The proposed model has the advantages of being simple and compact. It was validated using TCAD simulation results of the same transistor realized with Silvaco Software.
    Źródło:
    International Journal of Electronics and Telecommunications; 2021, 67, 4; 609--614
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Low Power, High Dynamic Range Analogue Multiplexer for Multi-Channel Parallel Recording of Neuronal Signals Using Multi-Electrode Arrays
    Autorzy:
    Rydygier, P.
    Dąbrowski, W.
    Fiutowski, T.
    Wiącek, P.
    Powiązania:
    https://bibliotekanauki.pl/articles/226679.pdf
    Data publikacji:
    2010
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    analogue multiplexer
    low power amplifier
    multi-channel electronics
    multielectrode arrays
    neural signal
    Opis:
    In the paper we present the design and test resultsof an integrated circuit combining a sample & hold circuit andan analogue multiplexer. The circuit has been designed as abuilding block for a multi-channel Application Specific IntegratedCircuit (ASIC) for recording signals from alive neuronal tissueusing high-density micro-electrode arrays (MEAs). The designis optimised with respect to critical requirements for suchapplications, i.e. short sampling time, low power dissipation, goodl inearity and high dynamic range. Presented design comprisessample&hold circuits with class AB operational amplifier, novelshift register, which allows minimising cross-coupling of the clocksignal and control logic. The circuit has been designed in 0.35µm CMOS process and has been successfully implemented in aprototype multi-channel ASIC.
    Źródło:
    International Journal of Electronics and Telecommunications; 2010, 56, 4; 399-404
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Design of an Ultra-Low Power CT Σ∆ A/D Modulator in 65nm CMOS for Cardiac Pacemakers: From System Synthesis to Circuit Implementation
    Autorzy:
    Wang, Y.
    Cai, H.
    Powiązania:
    https://bibliotekanauki.pl/articles/226202.pdf
    Data publikacji:
    2014
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    cardiac pacemaker
    CMOS
    ultra-low power
    analogue-to-digital
    Sigma-Delta modulation
    continuous-time
    Opis:
    A high performance, ultra-low power, fully differentia 2nd-order continuous-time Σ∆ analogue-to-digital modulator for cardiac pacemakers is presented in this paper. The entire design procedure is described in detail from the high-level system synthesis in both discrete and continuous-time domain, to the low-level circuit implementation of key functional blocks of the modulator. The power consumption of the designed modulator is rated at 182nA from a 1.2V power supply, meeting the ultra-low power requirement of the cardiac pacemaker applications. A 65nm CMOS technology is employed to implement the Σ∆ modulator. The modulator achieves a simulated SNR of 53.8dB over a 400 Hz signal bandwidth, with 32KHz sampling frequency and an oversampling ratio of 40. The active area of the modulator is 0.45×0.50mm².
    Źródło:
    International Journal of Electronics and Telecommunications; 2014, 60, 1; 109-115
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Study of a High-voltage Switching Power Supply Parameters
    Autorzy:
    Martemianov, Boris
    Ryzhkov, Alexander
    Vdovin, Grigoriy
    Powiązania:
    https://bibliotekanauki.pl/articles/2055213.pdf
    Data publikacji:
    2021
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    high voltage
    low power
    power supply
    microchannel plate
    MCP
    MCP detector
    low signal
    Cockcroft-Walton
    voltage multiplier
    pulse generator
    pulse transformer
    voltage stabilizer
    Opis:
    A principle diagram of a high-voltage low-power power supply for devices comprising a microchannel plate (MCP) has been developed. A mathematical model was built according to the developed scheme for a detailed study of the operation of the power supply and the selection of the optimal parameters of its components and obtaining the best output voltages. The power supply circuit comprises a control circuit, a pulse transformer, a voltage multiplier circuit, a feedback circuit, and an input stabilizer. The input stabilizer provides the maintenance of the voltage switched in the primary winding of the transformer at a given level regardless of the voltage drop of the power supply primary source. Moreover the stabilizer provides constant voltage maintenance when the load resistance changes. (with Rload changing from 100 to 200 MΩ, Uout did not exceed 3 V).
    Źródło:
    International Journal of Electronics and Telecommunications; 2021, 67, 4; 711--716
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Ultra Low Power Design for Digital CMOS Circuits Operating Near Threshold
    Autorzy:
    Kalra, S.
    Bhattacharyya, A. B.
    Powiązania:
    https://bibliotekanauki.pl/articles/226500.pdf
    Data publikacji:
    2017
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    energy efficiency
    ultra-low power
    EKV
    minimum energy point
    minimum delay point temperature to time generator
    Opis:
    Circuits operating in the subthreshold region are synonymous to low energy operation. However, the penalty in performance is colossal. In this paper, we investigate how designing in moderate inversion region recuperates some of that lost performance, while remaining very near to the minimum energy point. An α power based minimum energy delay modeling that is continuous over the weak, moderate, and strong inversion regions is presented. The value of α is obtained through interpolation following EKV model. The effect of supply voltage and device sizing on the minimum energy and performance is determined. The proposed model is utilized to design a temperature to time generator at 32nm technology node as the application of the proposed model. The abstract goes here.
    Źródło:
    International Journal of Electronics and Telecommunications; 2017, 63, 4; 369-374
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Enhancing IoT Performance via Using Mobility Aware for Dynamic RPL Routing Protocol Technique (MA-RPL)
    Autorzy:
    Zarzoor, Ahmed R.
    Powiązania:
    https://bibliotekanauki.pl/articles/2055261.pdf
    Data publikacji:
    2022
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    internet of things
    IoTs
    routing protocol for low power and lossy networks
    RPL
    mobility aware
    MA-RPL
    time difference of arrival
    TDoA
    Opis:
    Nodes' aware-mobility in the Internet of Things (IoTs) stills open defy for researchers, due to the dynamic changing of routing path and networks’ resource limitations. Therefore, in this study a new method is proposed called Mobility Aware - “Routing Protocol for Low power and Lossy Networks” (MARPL), that consists of two phases: in the first phase splitting the entire network into sub areas based on reference nodes with “Time Difference of Arrival” (TDoA) technique. While, the second phase, is about managing mobile nodes (MNs) in RPL according to the sub areas' ID. The Cooja simulator software has been used to implement and assess MA-RPL method performance, according to the data packet metrics (lost packet, packet delivery ratio PDR), latency and nodes' power usage in comparison with two methods: Corona (Co-RPL) and Mobility Enhanced (ME-RPL). The simulation results have been shown that the MA-RPL method consumes less nodes' energy usage, gives less latency with minimum data packet loss in comparison with Co-RPL and MERPL.
    Źródło:
    International Journal of Electronics and Telecommunications; 2022, 68, 2; 187--191
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-12 z 12

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