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Wyświetlanie 1-15 z 36
Tytuł:
On Transformation of a Logical Circuit to a Circuit with NAND and NOR Gates Only
Autorzy:
Baranov, S.
Karatkevich, A.
Powiązania:
https://bibliotekanauki.pl/articles/963932.pdf
Data publikacji:
2018
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
logic synthesis
logic devices
VLSI
minimization
Opis:
In the paper we consider fast transformation of a multilevel and multioutput circuit with AND, OR and NOT gates into a functionally equivalent circuit with NAND and NOR gates. The task can be solved by replacing AND and OR gates by NAND or NOR gates, which requires in some cases introducing the additional inverters or splitting the gates. In the paper the quick approximation algorithms of the circuit transformation are proposed, minimizing number of the inverters. The presented algorithms allow transformation of any multilevel circuit into a circuit being a combination of NOR gates, NAND gates or both types of universal gates.
Źródło:
International Journal of Electronics and Telecommunications; 2018, 64, 3; 373-378
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
High-Performance Ternary (4:2) Compressor Based on Capacitive Threshold Logic
Autorzy:
Mirzaee, R. F.
Reza, A.
Powiązania:
https://bibliotekanauki.pl/articles/225977.pdf
Data publikacji:
2017
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
4:2 compressor
ternary logic
multiple-valued logic
CNFET
threshold logic
Opis:
This paper presents a ternary (4:2) compressor, which is an important component in multiplication. However, the structure differs from the binary counterpart since the ternary model does not require carry signals. The method of capacitive threshold logic (CTL) is used to achieve the output signals directly. Unlike the previously presented similar structure, the entire capacitor network is divided into two parts. This segregation results in higher reliability and robustness against unwanted process, voltage, and temperature (PVT) variations. Simulations are performed by HSPICE and 32nm CNFET technology. Simulation results demonstrate about 94% higher performance in terms of power-delay product (PDP) for the new design over the previous one.
Źródło:
International Journal of Electronics and Telecommunications; 2017, 63, 4; 355-361
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Experimental Comparison of Synthesis Tools Altera Quartus II and Synthagate
Autorzy:
Węgrzyn, M.
Karatkevich, A.
Powiązania:
https://bibliotekanauki.pl/articles/226665.pdf
Data publikacji:
2013
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
logic design
state machines
logic devices
FPGA
VHDL
Opis:
The paper presents comparison between efficiency of an industrial FPGA design software tool Altera Quartus II and similar design software tool Synthagate by Syntezza company of an academic origin. The experiments were performed using a series of examples describing the Mealy finite state machines; onehot state encoding was used in all cases. Area (number of used logical blocks) was the main parameter used for the comparison. Influence of the way of FSM description (in VHDL language) on the quality of synthesis was studied. The obtained results show that Synthagate in almost all cases performs synthesis more efficiently and essentially quicker than Altera Quartus. Section I presents motivation of the research. Section II reminds the notion of FSM. Section III describes problems which had to be solved to provide correctness of experimental comparison. Section IV presents some details about state encoding way used in the experiments. In Section V, the experimental results are presented. Section VI describes the problems related to the comparison which still have to be solved. Section VII presents the conclusions from the experiments. Section VIII suggests possible reasons of the detected situation.
Źródło:
International Journal of Electronics and Telecommunications; 2013, 59, 4; 357-362
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Application of Indexed Partition Calculus in Logic Synthesis of Boolean Functions for FPGAs
Autorzy:
Rawski, M.
Powiązania:
https://bibliotekanauki.pl/articles/226483.pdf
Data publikacji:
2011
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
indexed partition
logic synthesis
FPGA
Opis:
Functional decomposition of Boolean functions specified by cubes proved to be very efficient. Most popular decomposition methods are based on blanket calculus. However computation complexity of blanket manipulations strongly depends on number of function's variables, which prevents them from being used for large functions of many input and output variables. In this paper a new concept of indexed partition is proposed and basic operations on indexed partitions are defined. Application of this concept to logic synthesis based on functional decomposition is also discussed. The experimental results show that algorithms based on new concept are able to deliver good quality solutions even for large functions and does it many times faster than the algorithms based on blanket calculus.
Źródło:
International Journal of Electronics and Telecommunications; 2011, 57, 2; 209-216
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Analysis of High-Performance Near-threshold Dual Mode Logic Design
Autorzy:
Bikki, Pavankumar
Powiązania:
https://bibliotekanauki.pl/articles/226748.pdf
Data publikacji:
2019
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
CMOS logic
dual mode logic
dynamic mode
high performance
minimum energy point
near-threshold
Opis:
A novel dual mode logic (DML) model has a superior energy-performance compare to CMOS logic. The DML model has unique feature that allows switching between both modes of operation as per the real-time system requirements. The DML functions in two dissimilar modes (static and dynamic) of operation with its specific features, to selectively obtain either low-energy or high-performance. The sub-threshold region DML achieves minimum-energy. However, sub-threshold region consequence in performance is enormous. In this paper, the working of DML model in the moderate inversion region has been explored. The near-threshold region holds much of the energy saving of subthreshold designs, along with improved performance. Furthermore, robustness to supply voltage and sensitivity to the process temperature variations are presented. Monte carol analysis shows that the projected near-threshold region has minimum energy along with the moderate performance.
Źródło:
International Journal of Electronics and Telecommunications; 2019, 65, 4; 723-729
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Synthesis of Macro Petri Nets into FPGA with Distributed Memories
Autorzy:
Bukowiec, A.
Adamski, M.
Powiązania:
https://bibliotekanauki.pl/articles/226342.pdf
Data publikacji:
2012
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
decomposition
FGPAs
logic synthesis
Petri nets
Opis:
In this paper a new method of Petri net array-based synthesis is proposed. The method is based on decomposition of colored interpreted macro Petri net into state machine subnets. Each state machine subnet is determined by one color. During the decomposition process macroplaces are expanded or replaced by doublers of macroplace. Such decomposition leads to parallel implementation of a digital system. The structured encoding of places is done by using minimal numbers of bits. Colored microoperations, which are assigned to places, are written into distributed and flexible memories. It leads to realization of a logic circuit in a two-level concurrent structure, where the combinational circuit of the first level is responsible for firing transitions, and the second level memories are used for generation of microoperations. Such an approach allows balanced usage of different kinds of resources available in modern FPGAs.
Źródło:
International Journal of Electronics and Telecommunications; 2012, 58, 4; 403-410
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Design Protection Using Logic Encryption and Scan-Chain Obfuscation Techniques
Autorzy:
Deepak, V. A.
Priyatharishini, M.
Devi, M. Nirmala
Powiązania:
https://bibliotekanauki.pl/articles/963795.pdf
Data publikacji:
2019
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
hardware security
obfuscation
logic encryption
scan-chain
Opis:
Due to increase in threats posed by offshore foundries, the companies outsourcing IPs are forced to protect their designs from the threats posed by the foundries. Few of the threats are IP piracy, counterfeiting and reverse engineering. To overcome these, logic encryption has been observed to be a leading countermeasure against the threats faced. It introduces extra gates in the design, known as key gates which hide the functionality of the design unless correct keys are fed to them. The scan tests are used by various designs to observe the fault coverage. These scan chains can become vulnerable to side-channel attacks. The potential solution for protection of this vulnerability is obfuscation of the scan output of the scan chain. This involves shuffling the working of the cells in the scan chain when incorrect test key is fed. In this paper, we propose a method to overcome the threats posed to scan design as well as the logic circuit. The efficiency of the secured design is verified on ISCAS’89 circuits and the results prove the security of the proposed method against the threats posed.
Źródło:
International Journal of Electronics and Telecommunications; 2019, 65, 3; 389-396
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Implementation of Algorithm of Petri Nets Distributed Synthesis into FPGA
Autorzy:
Bukowiec, A.
Tkacz, J.
Gratkowski, T.
Gidlewicz, T.
Powiązania:
https://bibliotekanauki.pl/articles/226156.pdf
Data publikacji:
2013
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
C#
decomposition
FGPA
logic synthesis
Petri net
Opis:
In the paper an implementation of algorithm of Petri net array-based synthesis is presented. The method is based on decomposition of colored interpreted macro Petri net into subnets. The structured encoding of places in subnets is done of using minimal numbers of bits. Microoperations, which are assigned to places, are written into distributed and flexible memories. It leads to realization of a logic circuit in a twolevel concurrent structure, where the combinational circuit of the first level is responsible for firing transitions, and the second level memories are used for generation of microoperations. This algorithm is implemented in C# and delivered as a stand alone library.
Źródło:
International Journal of Electronics and Telecommunications; 2013, 59, 4; 317-324
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Conception of Magnetic Memory Switched by Time Dependant Current Density and Current Electron Spin Polarization
Autorzy:
Steblinski, Paul
Blachowicz, Tomasz
Powiązania:
https://bibliotekanauki.pl/articles/227198.pdf
Data publikacji:
2019
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
spintronics
magnetic logic
BPM memories
magnetic simulations
Opis:
In this article the magnetic memory model with nano-meter size made from iron cells was proposed. For a purpose of determining the model specifications, the magnetic probes group with different geometrical parameters were examined using numeric simulations for the two different time duration of transitions among quasi-stable magnetic distributions found in the system, derived from the energy minimums. The geometrical parameters range was found, for which the 16 quasi–stable energetic states exist for the each probe. Having considered these results the 4 bits magnetic cells systems can be designed whose state is changed by spin-polarized current. Time dependent current densities and the current electron spin polarization directions were determined for all cases of transitions among quasi-stable states, for discovered set of 4 bits cells with different geometrical parameters. The 16-states cells, with the least geometrical area, achieved the 300 times bigger writing density in comparison to actual semiconductor solutions with the largest writing densities. The transitions among quasi-stable states of cells were examined for the time durations 10⁵ times shorter than that for up to date solutions.
Źródło:
International Journal of Electronics and Telecommunications; 2019, 65, 2; 309-312
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Graphical Method of Reversible Circuits Synthesis
Autorzy:
Skorupski, A.
Powiązania:
https://bibliotekanauki.pl/articles/226489.pdf
Data publikacji:
2017
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
reversible logic
reversible circuits
reversible gates
Toffoli gates
Opis:
This paper presents a new approach to designing reversible circuits. Reversible circuits can decrease energy dissipation theoretically to zero. This feature is a base to build quantum computers. The main problem of reversible logic is designing optimal reversible circuits i.e. circuits with minimal gates number implementing the given reversible function. There are many types of reversible gates. Most popular library is a set of three types of gates so called CNT (Control, NOT and Toffoli). The method presented in this paper is based only on the Toffoli gates. A graphical representation of the reversible function called s-maps is introduced in the paper. This representation allows to find optimal reversible circuits. The paper is organized as follows. Section 1 recalls basic concepts of reversible logic. In Section 2 a graphical representation of the reversible functions is presented. Section 3 describes the algorithm whereby all optimal solutions of the given function could be obtained.
Źródło:
International Journal of Electronics and Telecommunications; 2017, 63, 3; 235-240
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Quality of Minimal Sets of Prime Implicants of Boolean Functions
Autorzy:
Prasad, V. C.
Powiązania:
https://bibliotekanauki.pl/articles/227310.pdf
Data publikacji:
2017
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
logic circuits
digital circuits
Boolean functions
minimal sets
Opis:
Two new problems are posed and solved concerning minimal sets of prime implicants of Boolean functions. It is well known that the prime implicant set of a Boolean function should be minimal and have as few literals as possible. But it is not well known that min term repetitions should also be as few as possible to reduce power consumption. Determination of minimal sets of prime implicants is a well known problem. But nothing is known on the least number of (i) prime implicants (ii) literals and (iii) min term repetitions , any minimal set of prime implicants will have. These measures are useful to assess the quality of a minimal set. They are then extended to determine least number of prime implicants / implicates required to design a static hazard free circuit. The new technique tends to give smallest set of prime implicants for various objectives.
Źródło:
International Journal of Electronics and Telecommunications; 2017, 63, 2; 165-169
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Low Power and Improved Speed Montgomery Multiplier using Universal Building Blocks
Autorzy:
Velrajkumar, P.
Senthilpari, C.
Francisca, J. Sheela
Raj, T. Nirmal
Powiązania:
https://bibliotekanauki.pl/articles/226056.pdf
Data publikacji:
2019
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
FPGA
model sim
power dissipation
speed
universal logic
Opis:
This paper describes the arithmetic blocks based on Montgomery Multiplier (MM), which reduces complexity, gives lower power dissipation and higher operating frequency. The main objective in designing these arithmetic blocks is to use modified full adder structure and carry save adder structure that can be implemented in algorithm based MM circuit. The conventional full adder design acts as a benchmark for comparison, the second is the modified Boolean equation for full adder and third design is the design of full adder consisting of two XOR gate and a 2-to-1 Multiplexer. Besides Universal gates such as NOR gate and NAND gate, full adder circuits are used to further improve the speed of the circuit. The MM circuit is evaluated based on different parameters such as operating frequency, power dissipation and area of occupancy in FPGA board. The schematic designs of the arithmetic components along with the MM architecture are constructed using Quartus II tool, while the simulation is done using Model sim for verification of circuit functionality which has shown improvement on the full adder design with two XOR gate and one 2-to-1 Multiplexer implementation in terms of power dissipation, operating frequency and area.
Źródło:
International Journal of Electronics and Telecommunications; 2019, 65, 3; 477-483
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
A New Trust Framework for E-Government in Cloud of Things
Autorzy:
Abualese, Hasan
Al-Rousan, Thamer
Al-Shargabi, Bassam
Powiązania:
https://bibliotekanauki.pl/articles/226446.pdf
Data publikacji:
2019
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
cloud of things
e-government
fuzzy logic
trust
Opis:
The idea of using the Cloud of Things is becoming more critical for e-government, as it is considered to be a useful mechanism of facilitating the government’s work. The most important benefit of using the Cloud of Things concept is the increased productivity that the e-governments would achieve; which eventually would lead to significant cost savings; which in turn would have a highly anticipated future impact on egovernments. E-government’s diversity goals face many challenges; trust is one of the major challenges that it is facing when deploying the Cloud of Things. In this study, a new trust framework is proposed which supports trust with the Internet of Things devices interconnected to the cloud; to support the services that are provided by e-government to be delivered in a trusted manner. The proposed framework has been applied to a use case study to ensure its trustworthiness in a real mission. The results show that the proposed trust framework is useful to ensure achieving a trusted environment for the Cloud of Things for it to continue providing and gathering the data needed for the services that are offered by users through E-government.
Źródło:
International Journal of Electronics and Telecommunications; 2019, 65, 3; 397-405
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Partial Reconfiguration in the Field of Logic Controllers Design
Autorzy:
Doligalski, M.
Bukowiec, A.
Powiązania:
https://bibliotekanauki.pl/articles/227174.pdf
Data publikacji:
2013
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
HCfgPN
UML state machine diagram
Verilog
logic controller
Opis:
The paper presents method for logic controllers multi context implementation by means of partial reconfiguration. The UML state machine diagram specifies the behaviour of the logic controller. Multi context functionality is specified at the specification level as variants of the composite state. Each composite state, both orthogonal or compositional, describes specific functional requirement of the control process. The functional decomposition provided by composite states is required by the dynamic partial reconfiguration flow. The state machines specified by UML state machine diagrams are transformed into hierarchical configurable Petri nets (HCfgPN). HCfgPN are a Petri nets variant with the direct support of the exceptions handling mechanism. The paper presents placesoriented method for HCfgPN description in Verilog language. In the paper proposed methodology was illustrated by means of simple industrial control process.
Źródło:
International Journal of Electronics and Telecommunications; 2013, 59, 4; 351-356
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
K-Means and Fuzzy based Hybrid Clustering Algorithm for WSN
Autorzy:
Angadi, Basavaraj M.
Kakkasageri, Mahabaleshwar S.
Powiązania:
https://bibliotekanauki.pl/articles/27311955.pdf
Data publikacji:
2023
Wydawca:
Polska Akademia Nauk. Czasopisma i Monografie PAN
Tematy:
wireless sensor networks
cluster
K-Means algorithm
fuzzy logic
Opis:
Wireless Sensor Networks (WSN) acquired a lot of attention due to their widespread use in monitoring hostile environments, critical surveillance and security applications. In these applications, usage of wireless terminals also has grown significantly. Grouping of Sensor Nodes (SN) is called clustering and these sensor nodes are burdened by the exchange of messages caused due to successive and recurring re-clustering, which results in power loss. Since most of the SNs are fitted with nonrechargeable batteries, currently researchers have been concentrating their efforts on enhancing the longevity of these nodes. For battery constrained WSN concerns, the clustering mechanism has emerged as a desirable subject since it is predominantly good at conserving the resources especially energy for network activities. This proposed work addresses the problem of load balancing and Cluster Head (CH) selection in cluster with minimum energy expenditure. So here, we propose hybrid method in which cluster formation is done using unsupervised machine learning based kmeans algorithm and Fuzzy-logic approach for CH selection.
Źródło:
International Journal of Electronics and Telecommunications; 2023, 69, 4; 793--801
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Wyświetlanie 1-15 z 36

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