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    Wyświetlanie 1-8 z 8
    Tytuł:
    Performance Comparison of Stacked Dual-Metal Gate Engineered Cylindrical Surrounding Double-Gate MOSFET
    Autorzy:
    Dargar, Abha
    Srivastava, Viranjay M.
    Powiązania:
    https://bibliotekanauki.pl/articles/1844602.pdf
    Data publikacji:
    2021
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    short-channel effects
    metal oxide semiconductor
    transistor
    cylindrical surrounding double-gate
    dual-material gate
    microelectronics
    nanotechnology
    Opis:
    In this research work, a Cylindrical Surrounding Double-Gate (CSDG) MOSFET design in a stacked-Dual Metal Gate (DMG) architecture has been proposed to incorporate the ability of gate metal variation in channel field formation. Further, the internal gate's threshold voltage (VTH1) could be reduced compared to the external gate (VTH2) by arranging the gate metal work-function in Double Gate devices. Therefore, a device design of CSDG MOSFET has been realized to instigate the effect of Dual Metal Gate (DMG) stack architecture in the CSDG device. The comparison of device simulation shown optimized electric field and surface potential profile. The gradual decrease of metal work function towards the drain also improves the Drain Induced Barrier Lowering (DIBL) and subthreshold characteristics. The physics-based analysis of gate stack CSDG MOSFET that operates in saturation involving the analogy of cylindrical dual metal gates has been considered to evaluate the performance improvements. The insights obtained from the results using the gate-stack dual metal structure of CSDG are quite promising, which can serve as a guide to further reduce the threshold voltage roll-off, suppress the Hot Carrier Effects (HCEs) and Short Channel Effects (SCEs).
    Źródło:
    International Journal of Electronics and Telecommunications; 2021, 67, 1; 29-34
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Double-gate MOSFET Model Implemented in Verilog-AMS Language for the Transient Simulation and the Configuration of Ultra Low-power Analog Circuits
    Autorzy:
    Smaani, Billel
    Meraihi, Yacin
    Nafa, Fares
    Benlatreche, Mohamed Salah
    Akroum, Hamza
    Latreche, Saida
    Powiązania:
    https://bibliotekanauki.pl/articles/2055208.pdf
    Data publikacji:
    2021
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    double-gate MOSFET
    compact model
    ultra low power analog circuits
    Opis:
    This paper deals with the implementation of a DC and AC double-gate MOSFET compact model in the Verilog-AMS language for the transient simulation and the configuration of ultra low-power analog circuits. The Verilog-AMS description of the proposed model is inserted in SMASH circuit simulator for the transient simulation and the configuration of the Colpitts oscillator, the common-source amplifier, and the inverter. The proposed model has the advantages of being simple and compact. It was validated using TCAD simulation results of the same transistor realized with Silvaco Software.
    Źródło:
    International Journal of Electronics and Telecommunications; 2021, 67, 4; 609--614
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    The Algorithm for Reversible Circuits Synthesis
    Autorzy:
    Skorupski, Andrzej
    Gracki, Krzysztof
    Powiązania:
    https://bibliotekanauki.pl/articles/226226.pdf
    Data publikacji:
    2020
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    reversible logic
    reversible circuits
    reversible gate
    CNT set of the gates
    Opis:
    In this paper the new synthesis method for reversible networks is proposed. The method is suitable to generate optimal circuits. The examples will be shown for three variables reversible functions but the method is scalable to larger number of variables. The algorithm could be easily implemented with high speed execution and without big consuming storage software. Section 1 contains general concepts about the reversible functions. In Section 2 there are presented various descriptions of reversible functions. One of them is the description using partitions. In Section 3 there are introduced the cascade of the reversible gates as the target of the synthesis algorithm. In order to achieve this target the definitions of the rest and remain functions will be helpful. Section 4 contains the proposed algorithm. There is introduced a classification of minterms distribution for a given function. To select the successive gates in the cascade the condition of the improvement the minterms distribution must be fulfilled. Section 4 describes the algorithm how to improve the minterms distributions in order to find the optimal cascade. Section 5 shows the one example of this algorithm.
    Źródło:
    International Journal of Electronics and Telecommunications; 2020, 66, 2; 281-286
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    The Transforming Method Between Two Reversible Functions
    Autorzy:
    Skorupski, Andrzej
    Gracki, Krzysztof
    Powiązania:
    https://bibliotekanauki.pl/articles/226430.pdf
    Data publikacji:
    2019
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    reversible logic
    reversible circuits
    reversible gate
    CNT set of the gates
    Opis:
    This paper presents an original method of designing some special reversible circuits. This method is intended for the most popular gate set with three types of gates CNT (Control, NOT and Toffoli). The presented algorithm is based on two types of cascades with these reversible gates. The problem of transformation between two reversible functions is solved. This method allows to find optimal reversible circuits. The paper is organized as follows. Section 1 and 2 recalls basic concepts of reversible logic. Especially the two types of cascades of reversible function are presented. In Section 3 there is introduced a problem of analysis of the cascades. Section 4 describes the method of synthesis of the optimal cascade for transformation of the given reversible function into another one.
    Źródło:
    International Journal of Electronics and Telecommunications; 2019, 65, 1; 33-38
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Synthesis of FSMs Based on Architectural Decomposition with Joined Multiple Encoding
    Autorzy:
    Bukowiec, A.
    Powiązania:
    https://bibliotekanauki.pl/articles/227248.pdf
    Data publikacji:
    2012
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    Boolean algebra
    circuit synthesis
    field programmable gate array (FPGA)
    sequential circuits
    Opis:
    The method of synthesis of the logic circuit of finite state machine (FSM) with Mealy's outputs is proposed in this paper. Proposed method is based on the innovate encoding of microinstructions split into subsets. Code of microinstruction is represented as a part of current state code and code of microinstruction inside of current subset. It leads to realization of FSM as s double-level structure. It leads to diminishing of number of variables required for encoding of microinstructions. Such approach permits to decrease the number of required outputs of combinational part of FSM.
    Źródło:
    International Journal of Electronics and Telecommunications; 2012, 58, 1; 35-41
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    A Random Number Generator Using Ring Oscillators and SHA-256 as Post-Processing
    Autorzy:
    Łoza, S.
    Matuszewski, Ł.
    Jessa, M.
    Powiązania:
    https://bibliotekanauki.pl/articles/963943.pdf
    Data publikacji:
    2015
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    random numbers
    cryptography
    ring oscillators
    hash functions
    field programmable gate array (FPGA)
    Opis:
    Today, cryptographic security depends primarily on having strong keys and keeping them secret. The keys should be produced by a reliable and robust to external manipulations generators of random numbers. To hamper different attacks, the generators should be implemented in the same chip as a cryptographic system using random numbers. It forces a designer to create a random number generator purely digitally. Unfortunately, the obtained sequences are biased and do not pass many statistical tests. Therefore an output of the random number generator has to be subjected to a transformation called postprocessing. In this paper the hash function SHA-256 as postprocessing of bits produced by a combined random bit generator using jitter observed in ring oscillators (ROs) is proposed. All components – the random number generator and the SHA-256, are implemented in a single Field Programmable Gate Array (FPGA). We expect that the proposed solution, implemented in the same FPGA together with a cryptographic system, is more attack-resistant owing to many sources of randomness with significantly different nominal frequencies.
    Źródło:
    International Journal of Electronics and Telecommunications; 2015, 61, 2; 199-204
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    FPGA Implementation of Neural Nets
    Autorzy:
    Kumari, B A Sujatha
    Kulkarni, Sudarshan Patil
    Sinchana, C. G.
    Powiązania:
    https://bibliotekanauki.pl/articles/27311922.pdf
    Data publikacji:
    2023
    Wydawca:
    Polska Akademia Nauk. Czasopisma i Monografie PAN
    Tematy:
    artificial neural network
    Spartan-6
    field programmable gate arrays (FPGAs)
    convolutional neural network
    Opis:
    The field programmable gate array (FPGA) is used to build an artificial neural network in hardware. Architecture for a digital system is devised to execute a feed-forward multilayer neural network. ANN and CNN are very commonly used architectures. Verilog is utilized to describe the designed architecture. For the computation of certain tasks, a neural network’s distributed architecture structure makes it potentially efficient. The same features make neural nets suitable for application in VLSI technology. For the hardware of a neural network, a single neuron must be effectively implemented (NN). Reprogrammable computer systems based on FPGAs are useful for hardware implementations of neural networks.
    Źródło:
    International Journal of Electronics and Telecommunications; 2023, 69, 3; 599--604
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    An Efficient Classification of Hyperspectral Remotely Sensed Data Using Support Vector Machine
    Autorzy:
    Mahendra, H. N.
    Mallikarjunaswamy, S.
    Powiązania:
    https://bibliotekanauki.pl/articles/2134051.pdf
    Data publikacji:
    2022
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    support vector machine
    SVM
    central processing unit
    CPU
    digital signal processor
    DSP
    field programmable gate array
    FPGA
    high level synthesis
    HLS
    hardware description language
    HDL
    Opis:
    This work present an efficient hardware architecture of Support Vector Machine (SVM) for the classification of Hyperspectral remotely sensed data using High Level Synthesis (HLS) method. The high classification time and power consumption in traditional classification of remotely sensed data is the main motivation for this work. Therefore presented work helps to classify the remotely sensed data in real-time and to take immediate action during the natural disaster. An embedded based SVM is designed and implemented on Zynq SoC for classification of hyperspectral images. The data set of remotely sensed data are tested on different platforms and the performance is compared with existing works. Novelty in our proposed work is extend the HLS based FPGA implantation to the onboard classification system in remote sensing. The experimental results for selected data set from different class shows that our architecture on Zynq 7000 implementation generates a delay of 11.26 μs and power consumption of 1.7 Watts, which is extremely better as compared to other Field Programmable Gate Array (FPGA) implementation using Hardware description Language (HDL) and Central Processing Unit (CPU) implementation.
    Źródło:
    International Journal of Electronics and Telecommunications; 2022, 68, 3; 609--617
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-8 z 8

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