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    Wyświetlanie 1-10 z 10
    Tytuł:
    Influence of Drift on Efficiency of Optimal Analog Adaptive Communication Systems with Feedback and Its Compensation
    Autorzy:
    Jędrzejewski, K.
    Powiązania:
    https://bibliotekanauki.pl/articles/227312.pdf
    Data publikacji:
    2013
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    communication systems
    feedback
    drift compensation
    optimal adaptive estimation
    Opis:
    Results of analysis of drift influence on operation and efficiency of optimal analog adaptive communication systems with feedback and a new approach to drift compensation in these systems are presented in the paper. The proposed approach is based on application of the extended multidimensional adaptive algorithm that estimates simultaneously the value of a transmitted sample and the value of an unknown drift rate. The knowledge of the drift rate enables drift compensation and improves transmission efficiency of systems suffering problems related to drifts.
    Źródło:
    International Journal of Electronics and Telecommunications; 2013, 59, 1; 51-58
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Sinusoidal Oscillator Circuits Reexamined
    Autorzy:
    Prasad, V. C.
    Powiązania:
    https://bibliotekanauki.pl/articles/227105.pdf
    Data publikacji:
    2018
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    sinusoidal oscillator
    Barkhausen’s criterion
    analog circuits
    feedback circuits
    Opis:
    Singular network condition is proposed to study oscillators. It states that a circuit is a potential oscillator if and only if the rank of the network matrix of size n X n is (n -1) at the frequency of oscillations. The dual (if it exists) and adjoint circuit of an oscillator are also oscillators. Limitations of Barkhausen’s approach are pointed out. It is explained that there are many ways to generate oscillations other than Barkhausen’s positive feedback configuration. The new approach emphasizes that appropriate D C inputs / initial conditions are important.
    Źródło:
    International Journal of Electronics and Telecommunications; 2018, 64, 1; 77-81
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Scalable Method of Searching for Full-period Nonlinear Feedback Shift Registers with GPGPU : New List of Maximum Period NLFSRs
    Autorzy:
    Augustynowicz, P.
    Kanciak, K.
    Powiązania:
    https://bibliotekanauki.pl/articles/226184.pdf
    Data publikacji:
    2018
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    NLFSR
    GPGPU
    CUDA
    Nonlinear Feedback Shift Registers
    de Bruijn sequences
    Opis:
    This paper addresses the problem of efficient searching for Nonlinear Feedback Shift Registers (NLFSRs) with a guaranteed full period. The maximum possible period for an n-bit NLFSR is 2ⁿ - 1 (an all-zero state is omitted). A multi-stages hybrid algorithm which utilizes Graphics Processor Units (GPU) power was developed for processing data-parallel throughput computation. Usage of the abovementioned algorithm allows giving an extended list of n-bit NLFSR with maximum period for 7 cryptographically applicable types of feedback functions.
    Źródło:
    International Journal of Electronics and Telecommunications; 2018, 64, 2; 167-171
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Comparison of Different Wavelength Propagations over Few-Mode Fiber based on Space Division Multiplexing in Conjunction with Electrical Equalization
    Autorzy:
    Al-Dawoodi, A.
    Fareed, A.
    Masuda, T.
    Ghazi, A.
    Fakhrudeen, A. M.
    Aljunid, S. A.
    Idrus, S. Z. S.
    Amphawan, A.
    Powiązania:
    https://bibliotekanauki.pl/articles/226328.pdf
    Data publikacji:
    2019
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    few-mode fiber
    nonlinear distortions
    decision feedback equalizer
    eye diagram
    BER
    Opis:
    Nonlinearities in optical fibers deteriorate system performances and become a major performance-limiting issue. This article aims to investigate the compensation of nonlinear distortions in optical communication systems based on different wavelength propagations over few-mode fiber (FMF). The study adopted Space Division Multiplexing (SDM) based on decision feedback equalizer (DFE). Various transmission wavelength of the FMF system is applied to mitigate the attenuation effect on the system. In this paper, different wavelengths (780, 850 and 1550 nm) are used in SDM. Extensive simulation is performed to assess the attenuation and Bit Error Rate (BER) in each case. The results show that the wavelength of 1550 nm produces higher power and less attenuation in the transmission. Furthermore, this wavelength produces the best distance with less BER compared to 780 nm and 850 nm wavelengths. Moreover, the validations show improvement in BER and eye diagram.
    Źródło:
    International Journal of Electronics and Telecommunications; 2019, 65, 1; 5-10
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Loop Gain of the Common-Drain Colpitts Oscillator
    Autorzy:
    Kazimierczuk, M. K.
    Murthy-Bellur, D.
    Powiązania:
    https://bibliotekanauki.pl/articles/226711.pdf
    Data publikacji:
    2010
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    band-pass feedback networks
    Colpitts oscillator
    common-drain amplifier
    location of poles
    loop gain
    oscillation conditions
    positive feedback
    resonant oscillators
    tuned oscillators
    voltage-controlled oscillators (VCO)
    Opis:
    This paper presents the derivations of the voltage transfer functions of the amplifier A, the feedback network β, and the loop gain Τ of the common-drain (CD) Colpitts oscillator, using the small-signal model of the CD Colpitts oscillator. The derivation of the characteristic equation of the CD Colpitts oscillator is presented. Using the characteristic equation, the equation for the oscillation frequency of the sinusoidal output voltage and the condition for steady-state oscillation are derived. The characteristic equation is used to obtain a plot of trajectories of the poles of the CD Colpitts oscillator by varying the MOSFET small-signal transconductance gm. The locations of the complex conjugate poles depicting starting and steady-state conditions for oscillations are also presented.
    Źródło:
    International Journal of Electronics and Telecommunications; 2010, 56, 4; 423-426
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Logarithmic ADC with Accumulation of Charge and Impulse Feedback : Construction, Principle of Operation and Dynamic Properties
    Autorzy:
    Mychuda, Zynoviy
    Mychuda, Lesya
    Antoniv, Uliana
    Szcześniak, Adam
    Powiązania:
    https://bibliotekanauki.pl/articles/2055218.pdf
    Data publikacji:
    2021
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    analog-to-digital converter
    analysis
    construction
    charge accumulation
    logarithm
    modeling
    impulse feedback
    Opis:
    This article is a presentation of the analysis of new class of logarithmic analog-to-digital converter (LADC) with accumulation of charge and impulse feedback. LADC construction, principle of operation and dynamic properties were presented. They can also be part of more complex converters and systems based on LADC. LADC of this class is perspective for implementation in the form of integrated circuit, as the number of switched capacitors needed to conversion is minimized to one capacitor. (Logarithmic ADC with accumulation of charge and impulse feedback – construction, principle of operation and dynamic properties).
    Źródło:
    International Journal of Electronics and Telecommunications; 2021, 67, 4; 699--704
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Logarithmic ADC with Accumulation of Charge and Impulse Feedback : Analysis and Modeling
    Autorzy:
    Mychuda, Zynoviy
    Mychuda, Lesya
    Antoniv, Uliana
    Szcześniak, Adam
    Powiązania:
    https://bibliotekanauki.pl/articles/2055223.pdf
    Data publikacji:
    2021
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    analog-to-digital converter
    analysis
    construction
    charge accumulation
    logarithm
    modeling
    impulse feedback
    Opis:
    This article is a presentation of the analysis of new class of logarithmic analog-to-digital converter (LADC) with accumulation of charge and impulse feedback. Development of mathematical models of errors, quantitative assessment of these errors taking into account modern components and assessing the accuracy of logarithmic analog-to-digital converter (LADC) with accumulation of charge and impulse feedback were presented. (Logarithmic ADC with accumulation of charge and impulse feedback – analysis and modeling).
    Źródło:
    International Journal of Electronics and Telecommunications; 2021, 67, 4; 705--710
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Feasibility of FPGA to HPC computation migration of plasma impurities diagnostic algorithms
    Autorzy:
    Linczuk, P.
    Krawczyk, R. D.
    Zabolotny, W.
    Wojenski, A.
    Kolasinski, P.
    Pozniak, K. T.
    Kasprowicz, G.
    Chernyshova, M.
    Czarski, T.
    Powiązania:
    https://bibliotekanauki.pl/articles/226512.pdf
    Data publikacji:
    2017
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    plasma diagnostic
    GEM system
    feedback loops
    Intel Xeon
    Intel Xeon Phi
    high performance computing HPC
    Opis:
    We present a feasibility study of fast events parameters estimation algorithms regarding their execution time. It is the first stage of procedure used on data gathered from gas electron multiplier (GEM) detector for diagnostic of plasma impurities. Measured execution times are estimates of achievable times for future and more complex algorithms. The work covers usage of Intel Xeon and Intel Xeon Phi - high-performance computing (HPC) devices as a possible replacement for FPGA with highlighted advantages and disadvantages. Results show that less than 10 ms feedback loop can be obtained with the usage of 25% hardware resources in Intel Xeon or 10% resources in Intel Xeon Phi which leaves space for future increase of algorithms complexity. Moreover, this work contains a simplified overview of basic problems in actual measurement systems for diagnostic of plasma impurities, and emerging trends in developed solutions.
    Źródło:
    International Journal of Electronics and Telecommunications; 2017, 63, 3; 323-328
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Application of Digital Control Techniques for Satellite Medium Power DC-DC Converters
    Autorzy:
    Skup, K. R.
    Grudziński, P.
    Orleański, P.
    Powiązania:
    https://bibliotekanauki.pl/articles/226506.pdf
    Data publikacji:
    2011
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    DC-DC switching converter
    digital feedback loop
    FPGA
    VHDL
    digital current mode control
    digital voltage
    regulator
    bang-bang control
    digital PID
    PWM
    Opis:
    The objective of this paper is to present a work concerning a digital control loop system for satellite medium power DC-DC converters that is done in Space Research Centre. The whole control process of a described power converter is based on a high speed digital signal processing. The paper presents a development of a FPGA digital controller for voltage and current mode stabilization that was implemented using VHDL. The described controllers are based on a classical digital PID controller. The converter used for testing is a 200 kHz, 750W buck converter with 50V/15A output. A high resolution digital PWM approach is presented. Additionally a simple and effective solution of filtering of an analog-to-digital converter output is presented.
    Źródło:
    International Journal of Electronics and Telecommunications; 2011, 57, 1; 77-83
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    A 1.67 pJ/Conversion-step 8-bit SAR-Flash ADC Architecture in 90-nm CMOS Technology
    Autorzy:
    Khatak, Anil
    Kumar, Manoj
    Dhull, Sanjeev
    Powiązania:
    https://bibliotekanauki.pl/articles/1844527.pdf
    Data publikacji:
    2021
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    analog to digital converter
    ADC
    successive approximation register (SAR)
    common mode current feedback gain boosting
    CMFD-GB
    residue amplifier
    RA
    spurious free dynamic range
    SFDR
    integral nonlinearity
    INL
    differential nonlinearity
    DNL
    Opis:
    A novice advanced architecture of 8-bit analog to digital converter is introduced and analyzed in this paper. The structure of proposed ADC is based on the sub-ranging ADC architecture in which a 4-bit resolution flash-ADC is utilized. The proposed ADC architecture is designed by employing a comparator which is equipped with common mode current feedback and gain boosting technique (CMFD-GB) and a residue amplifier. The proposed 8 bits ADC structure can achieve the speed of 140 mega-samples per second. The proposed ADC architecture is designed at a resolution of 8 bits at 10 MHz sampling frequency. DNL and INL values of the proposed design are -0.94/1.22 and -1.19/1.19 respectively. The ADC design dissipates a power of 1.24 mW with the conversion speed of 0.98 ns. The magnitude of SFDR and SNR from the simulations at Nyquist input is 39.77 and 35.62 decibel respectively. Simulations are performed on a SPICE based tool in 90 nm CMOS technology. The comparison shows better performance for this proposed ADC design in comparison to other ADC architectures regarding speed, resolution and power consumption.
    Źródło:
    International Journal of Electronics and Telecommunications; 2021, 67, 3; 347-354
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-10 z 10

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