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Wyszukujesz frazę "digital signal processing." wg kryterium: Temat

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    Wyświetlanie 1-5 z 5
    Tytuł:
    Large Data Stream Processing : Embedded Systems Design Challenges
    Autorzy:
    Handzlik, A.
    Jabłonski, A.
    Powiązania:
    https://bibliotekanauki.pl/articles/226898.pdf
    Data publikacji:
    2010
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    reconfigurable hardware
    system on chip
    digital signal processing
    embedded systems
    Opis:
    The following paper describes an application of reconfigurable hardware architectures for processing of huge data streams. Radar, sonar and high speed internet networks are typical sources of data that require extreme computing power and resources to enable real time acquisition, processing and management. An approach to monitoring of real time multi-gigabit internet network has been described as a practical application of FPGA based board, designed for fast data processing.
    Źródło:
    International Journal of Electronics and Telecommunications; 2010, 56, 2; 107-110
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Construction of Generalized Rademacher Functions in Terms of Ternary Logic : Solving the Problem of Visibility of Using Galois Fields for Digital Signal Processing
    Autorzy:
    Vitulyova, Elizaveta S.
    Matrassulova, Dinara K.
    Suleimenov, Ibragim E.
    Powiązania:
    https://bibliotekanauki.pl/articles/2055235.pdf
    Data publikacji:
    2022
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    digital signal processing
    non-binary Galois fields
    fourier transform
    rademacher functions
    walsh function
    multivalued logic
    visibility problem
    algebraic extensions
    ternary representation of number
    Opis:
    Generalized Rademacher functions, constructed as a sequence of elements of Galois fields are intended to find the spectral representation of signals with levels. These functions form a complete basis on the interval corresponding to -1 discrete time intervals and for passing into the classical Rademacher functions. The advantage of such spectra obtained using Galois Fields Fourier Transform is that the range of variation of the spectrum amplitudes remains the same as the range of variation of the original signal, which is modeled on discrete time functions taking values in the Galois field.
    Źródło:
    International Journal of Electronics and Telecommunications; 2022, 68, 2; 237--244
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Modified Block Sparse Bayesian Learning-Based Compressive Sensing Scheme For EEG Signals
    Autorzy:
    Upadhyaya, Vivek
    Salim, Mohammad
    Powiązania:
    https://bibliotekanauki.pl/articles/1844532.pdf
    Data publikacji:
    2021
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    compressive sensing
    CS
    mean square error
    MSE
    structural similarity index measure
    SSIM
    electroencephalogram
    EEG
    digital signal processing
    DSP
    block sparse Bayesian learning
    BSBL
    Opis:
    Advancement in medical technology creates some issues related to data transmission as well as storage. In real-time processing, it is too tedious to limit the flow of data as it may reduce the meaningful information too. So, an efficient technique is required to compress the data. This problem arises in Magnetic Resonance Imaging (MRI), Electrocardiogram (ECG), Electroencephalogram (EEG), and other medical signal processing domains. In this paper, we demonstrate Block Sparse Bayesian Learning (BSBL) based compressive sensing technique on an Electroencephalogram (EEG) signal. The efficiency of the algorithm is described using the Mean Square Error (MSE) and Structural Similarity Index Measure (SSIM) value. Apart from this analysis we also use different combinations of sensing matrices too, to demonstrate the effect of sensing matrices on MSE and SSIM value. And here we got that the exponential and chi-square random matrices as a sensing matrix are showing a significant change in the value of MSE and SSIM. So, in real-time body sensor networks, this scheme will contribute a significant reduction in power requirement due to its data compression ability as well as it will reduce the cost and the size of the device used for real-time monitoring.
    Źródło:
    International Journal of Electronics and Telecommunications; 2021, 67, 3; 331-336
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Programmable, Asynchronous, Triangular Neighborhood Function for Self-Organizing Maps Realized on Transistor Level
    Autorzy:
    Kolasa, M.
    Długosz, R.
    Bieliński, K.
    Powiązania:
    https://bibliotekanauki.pl/articles/226845.pdf
    Data publikacji:
    2010
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    self-organizing maps
    parallel signal processing
    CMOS realization
    low energy consumption
    digital circuits
    Opis:
    A new hardware implementation of the triangular neighborhood function (TNF) for ultra-low power, Kohonen self-organizing maps (SOM) realized in the CMOS 0.18žm technology is presented. Simulations carried out by means of the software model of the SOM show that even low signal resolution at the output of the TNF block of 3-6 bits (depending on input data set) does not lead to significant disturbance of the learning process of the neural network. On the other hand, the signal resolution has a dominant influence on the overall circuit complexity i.e. the chip area and the energy consumption. The proposed neighborhood mechanism is very fast. For an example neighborhood range of 15 a delay between the first and the last neighboring neuron does not exceed 20 ns. This in practice means that the adaptation process starts in all neighboring neurons almost at the same time. As a result, data rates of 10-20 MHz are achievable, independently on the number of neurons in the map. The proposed SOM dissipates the power in-between 100 mW and 1 W, depending on the number of neurons in the map. For the comparison, the same network realized on PC achieves in simulations data rates in-between 10 Hz and 1 kHz. Data rate is in this case linearly dependend on the number of neurons.
    Źródło:
    International Journal of Electronics and Telecommunications; 2010, 56, 4; 367-373
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    An Efficient Classification of Hyperspectral Remotely Sensed Data Using Support Vector Machine
    Autorzy:
    Mahendra, H. N.
    Mallikarjunaswamy, S.
    Powiązania:
    https://bibliotekanauki.pl/articles/2134051.pdf
    Data publikacji:
    2022
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    support vector machine
    SVM
    central processing unit
    CPU
    digital signal processor
    DSP
    field programmable gate array
    FPGA
    high level synthesis
    HLS
    hardware description language
    HDL
    Opis:
    This work present an efficient hardware architecture of Support Vector Machine (SVM) for the classification of Hyperspectral remotely sensed data using High Level Synthesis (HLS) method. The high classification time and power consumption in traditional classification of remotely sensed data is the main motivation for this work. Therefore presented work helps to classify the remotely sensed data in real-time and to take immediate action during the natural disaster. An embedded based SVM is designed and implemented on Zynq SoC for classification of hyperspectral images. The data set of remotely sensed data are tested on different platforms and the performance is compared with existing works. Novelty in our proposed work is extend the HLS based FPGA implantation to the onboard classification system in remote sensing. The experimental results for selected data set from different class shows that our architecture on Zynq 7000 implementation generates a delay of 11.26 μs and power consumption of 1.7 Watts, which is extremely better as compared to other Field Programmable Gate Array (FPGA) implementation using Hardware description Language (HDL) and Central Processing Unit (CPU) implementation.
    Źródło:
    International Journal of Electronics and Telecommunications; 2022, 68, 3; 609--617
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-5 z 5

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