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    Wyświetlanie 1-4 z 4
    Tytuł:
    Modified Distributed Arithmetic Concept for Implementations Targeted at Heterogeneous FPGAs
    Autorzy:
    Rawski, M.
    Powiązania:
    https://bibliotekanauki.pl/articles/226835.pdf
    Data publikacji:
    2010
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    distributed arithmetic
    FPGA
    heterogeneous programmable structures
    Opis:
    Distributed Arithmetic (DA) plays an important role in designing digital signal processing modules for FPGA architectures. It allows replacing multiply-and-accumulate (MAC) operations with combinational blocks. The quality of implementations based on DA strongly depends on efficiency of methods that map combinational DA block into FPGA resources. Since modern FPGAs have heterogeneous structure, there is a need for quality algorithms to target these structures and the need for flexible architecture exploration aiding in appropriate mapping. The paper presents a modification of DA concept that allows for very efficient implementation in heterogeneous FPGA architectures.
    Źródło:
    International Journal of Electronics and Telecommunications; 2010, 56, 4; 345-350
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    High Performance DIF-FFT Using Dissimilar Partitioned LUT Based Distributed Arithmetic
    Autorzy:
    Cheepurupalli, Kusma Kumari
    Charan, Muntha
    Rao, Jammu Bhaskara
    Noor, Mahammad S.
    Powiązania:
    https://bibliotekanauki.pl/articles/2055270.pdf
    Data publikacji:
    2021
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    fast Fourier transform
    adders
    distributed arithmetic
    DSP
    Opis:
    Real-time data processing systems utilize Digital Signal Processing (DSP) functions as the base modules. Most of the DSP functions involve the implementation of Fast Fourier Transform (FFT) to convert the signals from one domain to another domain. The major bottleneck of Decimation in frequency - Fast Fourier Transform (DIF-FFT) implementation lies in using a number of Multipliers. Distributed arithmetic (DA) is considered as one of the efficient techniques to implement DIF-FFT. In this approach, the multipliers are not used. The proposed technique exploits the very advantage of the look-up table by storing the Twiddle factors, thereby avoiding the multipliers required in the butterfly structure. DIF-FFT using Distributed Arithmetic (DIF-FFT DA) models, with different adders such as Ripple carry adder (RCA), Carry-lookahead adder (CLA), and Sklansky prefix graph adder, are proposed in this paper. The three proposed models are synthesized using Cadence 6.1 EDA tools with a 45nm CMOS technology. Compared to the traditional method, it is observed that the area is improved by 53.11%, 53.35%, and 50.15%, power is improved by 42.31%, 42.52%, and 40.39%, and delay is improved by 45.26%, 45.42%, 41.80%, respectively.
    Źródło:
    International Journal of Electronics and Telecommunications; 2021, 67, 4; 631--637
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Modeling the Arithmetic Decomposition of DA-LUT Block for Heterogeneous FPGA Structures
    Autorzy:
    Staworko, M.
    Rawski, M.
    Powiązania:
    https://bibliotekanauki.pl/articles/226414.pdf
    Data publikacji:
    2012
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    distributed arithmetic
    FPGA
    FIR filter
    heterogeneous programmable structures
    Opis:
    Distributed arithmetic is well known technique of designing FIR filters in FPGA devices. The quality of such filter implementation strongly depends on synthesis results of the DALUT block. Heterogeneity of modern FPGA structures introduces new possibilities into implementation process, that may lead to better results, but also makes it more complicated. This paper presents the simple mathematical model for estimating the necessary FPGA resources to implement DA-LUT using decomposition-based approach. The model takes into account the type of logic cells or memory blocks used for decomposition process. The proposed model is help ful to determinate the DALUT decomposition strategy for further automation of modified distributed arithmetic decomposition method.
    Źródło:
    International Journal of Electronics and Telecommunications; 2012, 58, 4; 335-344
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Synthesis and Implementation of Reconfigurable PLC on FPGA Platform
    Autorzy:
    Milik, A.
    Hrynkiewicz, E.
    Powiązania:
    https://bibliotekanauki.pl/articles/226640.pdf
    Data publikacji:
    2012
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    PLC
    LD
    IL
    FPGA
    high level synthesis
    logic synthesis
    arithmetic circuits
    reconfigurable hardware
    Opis:
    The paper presents a set of algorithms dedicated for synthesis of reconfigurable logic controllers implemented on FPGA platform and programmed according to IEC1131 and EN61131. The program is compiled to hardware structure with a massive parallel processing. The developed method automatically allocates resources and operations. It controls resource usage and operation timing. Using mixed concept of operation allocation that considers operation timing and forms combinatorial chains of operations number of execution cycles can be reduced. An example of logic functions, PID controller and mixed arithmetic and logic programming examples are considered. Introducing the automatic implementation method allows flexible implementing the control algorithms. The maximal possible parallelism (limited only by the algorithm dependencies and available resources) is introduced.
    Źródło:
    International Journal of Electronics and Telecommunications; 2012, 58, 1; 85-94
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-4 z 4

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