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Wyszukujesz frazę "analog VLSI" wg kryterium: Temat


Wyświetlanie 1-2 z 2
Tytuł:
Fast Low Voltage Analog Four-Quadrant Multipliers Based on CMOS Inverters
Autorzy:
Machowski, W.
Kuta, S.
Jasielski, J.
Kołodziejski, W.
Powiązania:
https://bibliotekanauki.pl/articles/226683.pdf
Data publikacji:
2010
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
analog VLSI
four-quadrant multiplier
CMOS circuits
low voltage circuits
Opis:
The paper presents quarter-square analog four-quadrant multipliers, based on proprietary architecture using four CMOS inverters. The most important upgrade on already published own circuit implementation is the use of the same inverter "core" of the circuit with completely redesigned auxiliary and steering blocks. Two variants of new driving peripherals are considered: one with differential pair, the second with CMOS inverters. The proposed circuit solutions are suitable for RF applications in communication systems due to simple architecture comprising building blocks with RF CMOS transistors having sufficiently large biasing currents. Postlayout simulation results done on the basis of 180nm CMOS UMC Foundry Design Kit are also presented.
Źródło:
International Journal of Electronics and Telecommunications; 2010, 56, 4; 381-386
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Test Procedures for Synchronized Oscillators Network CMOS VLSI Chip
Autorzy:
Kowalski, J.
Strzelecki, M.
Powiązania:
https://bibliotekanauki.pl/articles/226984.pdf
Data publikacji:
2015
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
neural networks chip testing
synchronized oscillator network
parallel image segmentation
analog-digital VLSI CMOS implementation
Opis:
The paper presents test procedures designed for application - specific integrated circuit (ASIC) CMOS VLSI chip prototype that implements a synchronized oscillator neural network with a matrix size of 32×32 for object detecting in binary images. Networks of synchronized oscillators are recently developed tool for image segmentation and analysis. This paper briefly introduces synchronized oscillators network. Basic chip analog building blocks with their test procedures and measurements results are presented. In order to do measurements, special basic building blocks test structures have been implemented in the chip. It let compare Spectre simulateions results to measurements results. Moreover, basic chip analog building blocks measurements give precious information about their imperfections caused by MOS transistor mismatch. This information is very usable during design and improvement of a special setup for chip functional tests. Improvement of the setup is a digitally assisted analog technique. It is an original idea of oscillators tuning procedure used during chip prototype testing. Such setup, oscillators tuning procedure and segmentation of sample binary images are presented.
Źródło:
International Journal of Electronics and Telecommunications; 2015, 61, 1; 101-107
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
    Wyświetlanie 1-2 z 2

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