Temat: Sigma-Delta - Katalog OPAC zbiorów

Skocz do pozycji: 1.

Tytuł:: Switched Current Sigma-Delta Modulator with a New Comparator Structure Designed Based on VHDL-AMS Description
Autorzy:: Śniatała, P
Handkiewicz, A
Naumowicz, M.
Szczęsny, S.
Melosik, M.
Katarzyński, P.
Kropidłowski, M.
Powiązania:: https://bibliotekanauki.pl/articles/227188.pdf
Data publikacji:: 2013
Wydawca:: Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:: switched current
VHDL-AMS
sigma-delta modulator
Opis:: The paper presents a VHDL-AMS based approach to the Switched-Current (SI) Sigma-Delta Modulator design. The prototype VHDL-AMS description, with the help of elaborated EDA tools, is automatically translated into the SI realization. Another tool helps the designer to create the layout. The paper also describes a new current mode comparator, which is used in the design. Postlayout simulation results are presented.
Źródło:: International Journal of Electronics and Telecommunications; 2013, 59, 4; 391-396
2300-1933
Pojawia się w:: International Journal of Electronics and Telecommunications
Dostawca treści:: Biblioteka Nauki

Artykuł

Skocz do pozycji: 2.

Tytuł:: Rapid Prototyping of Third-Order Sigma-Delta A/D Converters
Autorzy:: Suszyński, R.
Wawryn, K.
Powiązania:: https://bibliotekanauki.pl/articles/226620.pdf
Data publikacji:: 2013
Wydawca:: Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:: sigma-delta converter
A/D converter
FPAA
MASH structure
Opis:: Prototyping ot third-order sigma-delta analog to dogital converters (ΣΔ ADCs) has been presented in the paper. The method is based on implementation of field programmable analog arrays (FPAA) to configure and reconfigure proposed circuits. Three third-order ΣΔ ADC structures have been considered. The circuit characteristics have been measured and then the structure of the converters have been reconfigured tro satisfy input specifications.
Źródło:: International Journal of Electronics and Telecommunications; 2013, 59, 1; 99-104
2300-1933
Pojawia się w:: International Journal of Electronics and Telecommunications
Dostawca treści:: Biblioteka Nauki

Artykuł

Skocz do pozycji: 3.

Tytuł:: Design of an Ultra-Low Power CT Σ∆ A/D Modulator in 65nm CMOS for Cardiac Pacemakers: From System Synthesis to Circuit Implementation
Autorzy:: Wang, Y.
Cai, H.
Powiązania:: https://bibliotekanauki.pl/articles/226202.pdf
Data publikacji:: 2014
Wydawca:: Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:: cardiac pacemaker
CMOS
ultra-low power
analogue-to-digital
Sigma-Delta modulation
continuous-time
Opis:: A high performance, ultra-low power, fully differentia 2nd-order continuous-time Σ∆ analogue-to-digital modulator for cardiac pacemakers is presented in this paper. The entire design procedure is described in detail from the high-level system synthesis in both discrete and continuous-time domain, to the low-level circuit implementation of key functional blocks of the modulator. The power consumption of the designed modulator is rated at 182nA from a 1.2V power supply, meeting the ultra-low power requirement of the cardiac pacemaker applications. A 65nm CMOS technology is employed to implement the Σ∆ modulator. The modulator achieves a simulated SNR of 53.8dB over a 400 Hz signal bandwidth, with 32KHz sampling frequency and an oversampling ratio of 40. The active area of the modulator is 0.45×0.50mm².
Źródło:: International Journal of Electronics and Telecommunications; 2014, 60, 1; 109-115
2300-1933
Pojawia się w:: International Journal of Electronics and Telecommunications
Dostawca treści:: Biblioteka Nauki

Artykuł

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