- Tytuł:
- Architecture Design of The Hardware H.264/AVC Video Decoder
- Autorzy:
-
Roszkowski, M.
Abramowski, A.
Wieczorek, M.
Pastuszak, G. - Powiązania:
- https://bibliotekanauki.pl/articles/226831.pdf
- Data publikacji:
- 2010
- Wydawca:
- Polska Akademia Nauk. Czytelnia Czasopism PAN
- Tematy:
-
H.264/AVC
video compression
FPGA
architecture design - Opis:
- The need for real-time video compression systems requires a particular design methodology to achieve high troughput devices. The paper describes the architecture of the H.264/AVC decoder able to support SDTV and HDTV resolutions. The design applies many optimization techniques to reduce the resource consumption and maximize the throughput. The archietcture is verified with the software reference model JM16 and synhesized for FPGA technology. The maximal working frequency is 100 MHz for Stratix II devices.
- Źródło:
-
International Journal of Electronics and Telecommunications; 2010, 56, 3; 291-300
2300-1933 - Pojawia się w:
- International Journal of Electronics and Telecommunications
- Dostawca treści:
- Biblioteka Nauki
Artykuł