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Wyświetlanie 1-15 z 42
Tytuł:
High-Performance Ternary (4:2) Compressor Based on Capacitive Threshold Logic
Autorzy:
Mirzaee, R. F.
Reza, A.
Powiązania:
https://bibliotekanauki.pl/articles/225977.pdf
Data publikacji:
2017
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
4:2 compressor
ternary logic
multiple-valued logic
CNFET
threshold logic
Opis:
This paper presents a ternary (4:2) compressor, which is an important component in multiplication. However, the structure differs from the binary counterpart since the ternary model does not require carry signals. The method of capacitive threshold logic (CTL) is used to achieve the output signals directly. Unlike the previously presented similar structure, the entire capacitor network is divided into two parts. This segregation results in higher reliability and robustness against unwanted process, voltage, and temperature (PVT) variations. Simulations are performed by HSPICE and 32nm CNFET technology. Simulation results demonstrate about 94% higher performance in terms of power-delay product (PDP) for the new design over the previous one.
Źródło:
International Journal of Electronics and Telecommunications; 2017, 63, 4; 355-361
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Analysis of High-Performance Near-threshold Dual Mode Logic Design
Autorzy:
Bikki, Pavankumar
Powiązania:
https://bibliotekanauki.pl/articles/226748.pdf
Data publikacji:
2019
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
CMOS logic
dual mode logic
dynamic mode
high performance
minimum energy point
near-threshold
Opis:
A novel dual mode logic (DML) model has a superior energy-performance compare to CMOS logic. The DML model has unique feature that allows switching between both modes of operation as per the real-time system requirements. The DML functions in two dissimilar modes (static and dynamic) of operation with its specific features, to selectively obtain either low-energy or high-performance. The sub-threshold region DML achieves minimum-energy. However, sub-threshold region consequence in performance is enormous. In this paper, the working of DML model in the moderate inversion region has been explored. The near-threshold region holds much of the energy saving of subthreshold designs, along with improved performance. Furthermore, robustness to supply voltage and sensitivity to the process temperature variations are presented. Monte carol analysis shows that the projected near-threshold region has minimum energy along with the moderate performance.
Źródło:
International Journal of Electronics and Telecommunications; 2019, 65, 4; 723-729
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
New Conception of Safety Logic Microcontroller
Autorzy:
Sałamaj, M.
Powiązania:
https://bibliotekanauki.pl/articles/226338.pdf
Data publikacji:
2012
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
safety logic microcontroller
critical systems
master-slave architecture
handshake
GALS
conception
Opis:
In this paper a new conception of safety logic microcontroller (BML) is described, together with its physical hardware realization. The unit has various mechanisms which increase its safety and reliability, so that it can satisfy rigorous requirements of safety-critical systems. Thus, the BML unit uses some untypical and innovative technical solutions. The new approach to safety systems development allowed to propose a new conception. The paper describes also physical realization of small multiprocessor BML unit for management of decision-control systems adopted to critical usage.
Źródło:
International Journal of Electronics and Telecommunications; 2012, 58, 4; 419-424
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Application of Indexed Partition Calculus in Logic Synthesis of Boolean Functions for FPGAs
Autorzy:
Rawski, M.
Powiązania:
https://bibliotekanauki.pl/articles/226483.pdf
Data publikacji:
2011
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
indexed partition
logic synthesis
FPGA
Opis:
Functional decomposition of Boolean functions specified by cubes proved to be very efficient. Most popular decomposition methods are based on blanket calculus. However computation complexity of blanket manipulations strongly depends on number of function's variables, which prevents them from being used for large functions of many input and output variables. In this paper a new concept of indexed partition is proposed and basic operations on indexed partitions are defined. Application of this concept to logic synthesis based on functional decomposition is also discussed. The experimental results show that algorithms based on new concept are able to deliver good quality solutions even for large functions and does it many times faster than the algorithms based on blanket calculus.
Źródło:
International Journal of Electronics and Telecommunications; 2011, 57, 2; 209-216
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
SMTBDD : New Form of BDD for Logic Synthesis
Autorzy:
Kubica, M.
Kania, D.
Powiązania:
https://bibliotekanauki.pl/articles/226064.pdf
Data publikacji:
2016
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
logic synthesis
SMTBDD
decomposition
technology mapping
FPGA
digital circuits
Opis:
The main purpose of the paper is to suggest a new form of BDD - SMTBDD diagram, methods of obtaining, and its basic features. The idea of using SMTBDD diagram in the process of logic synthesis dedicated to FPGA structures is presented. The creation of SMTBDD diagrams is the result of cutting BDD diagram which is the effect of multiple decomposition. The essence of a proposed decomposition method rests on the way of determining the number of necessary ‘g’ bounded functions on the basis of the content of a root table connected with an appropriate SMTBDD diagram. The article presents the methods of searching non-disjoint decomposition using SMTBDD diagrams. Besides, it analyzes the techniques of choosing cutting levels as far as effective technology mapping is concerned. The paper also discusses the results of the experiments which confirm the efficiency of the analyzed decomposition methods.
Źródło:
International Journal of Electronics and Telecommunications; 2016, 62, 1; 33-41
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Partial Reconfiguration in the Field of Logic Controllers Design
Autorzy:
Doligalski, M.
Bukowiec, A.
Powiązania:
https://bibliotekanauki.pl/articles/227174.pdf
Data publikacji:
2013
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
HCfgPN
UML state machine diagram
Verilog
logic controller
Opis:
The paper presents method for logic controllers multi context implementation by means of partial reconfiguration. The UML state machine diagram specifies the behaviour of the logic controller. Multi context functionality is specified at the specification level as variants of the composite state. Each composite state, both orthogonal or compositional, describes specific functional requirement of the control process. The functional decomposition provided by composite states is required by the dynamic partial reconfiguration flow. The state machines specified by UML state machine diagrams are transformed into hierarchical configurable Petri nets (HCfgPN). HCfgPN are a Petri nets variant with the direct support of the exceptions handling mechanism. The paper presents placesoriented method for HCfgPN description in Verilog language. In the paper proposed methodology was illustrated by means of simple industrial control process.
Źródło:
International Journal of Electronics and Telecommunications; 2013, 59, 4; 351-356
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Experimental Comparison of Synthesis Tools Altera Quartus II and Synthagate
Autorzy:
Węgrzyn, M.
Karatkevich, A.
Powiązania:
https://bibliotekanauki.pl/articles/226665.pdf
Data publikacji:
2013
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
logic design
state machines
logic devices
FPGA
VHDL
Opis:
The paper presents comparison between efficiency of an industrial FPGA design software tool Altera Quartus II and similar design software tool Synthagate by Syntezza company of an academic origin. The experiments were performed using a series of examples describing the Mealy finite state machines; onehot state encoding was used in all cases. Area (number of used logical blocks) was the main parameter used for the comparison. Influence of the way of FSM description (in VHDL language) on the quality of synthesis was studied. The obtained results show that Synthagate in almost all cases performs synthesis more efficiently and essentially quicker than Altera Quartus. Section I presents motivation of the research. Section II reminds the notion of FSM. Section III describes problems which had to be solved to provide correctness of experimental comparison. Section IV presents some details about state encoding way used in the experiments. In Section V, the experimental results are presented. Section VI describes the problems related to the comparison which still have to be solved. Section VII presents the conclusions from the experiments. Section VIII suggests possible reasons of the detected situation.
Źródło:
International Journal of Electronics and Telecommunications; 2013, 59, 4; 357-362
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Features Reduction Using Logic Minimization Techniques
Autorzy:
Borowik, G.
Łuba, T.
Zydek, D.
Powiązania:
https://bibliotekanauki.pl/articles/227282.pdf
Data publikacji:
2012
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
machine learning
knowledge representation
discernibility function
logic minimization
attribute reduction
complement
Opis:
This paper is dedicated to two seemingly different problems. The first one concerns information theory and the second one is connected to logic synthesis methods. The reason why these issues are considered together is the important task of the efficient representation of data in information systems and as well as in logic systems. An efficient algorithm to solve the task of attributes/arguments reduction is presented.
Źródło:
International Journal of Electronics and Telecommunications; 2012, 58, 1; 71-76
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Design Protection Using Logic Encryption and Scan-Chain Obfuscation Techniques
Autorzy:
Deepak, V. A.
Priyatharishini, M.
Devi, M. Nirmala
Powiązania:
https://bibliotekanauki.pl/articles/963795.pdf
Data publikacji:
2019
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
hardware security
obfuscation
logic encryption
scan-chain
Opis:
Due to increase in threats posed by offshore foundries, the companies outsourcing IPs are forced to protect their designs from the threats posed by the foundries. Few of the threats are IP piracy, counterfeiting and reverse engineering. To overcome these, logic encryption has been observed to be a leading countermeasure against the threats faced. It introduces extra gates in the design, known as key gates which hide the functionality of the design unless correct keys are fed to them. The scan tests are used by various designs to observe the fault coverage. These scan chains can become vulnerable to side-channel attacks. The potential solution for protection of this vulnerability is obfuscation of the scan output of the scan chain. This involves shuffling the working of the cells in the scan chain when incorrect test key is fed. In this paper, we propose a method to overcome the threats posed to scan design as well as the logic circuit. The efficiency of the secured design is verified on ISCAS’89 circuits and the results prove the security of the proposed method against the threats posed.
Źródło:
International Journal of Electronics and Telecommunications; 2019, 65, 3; 389-396
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
On Transformation of a Logical Circuit to a Circuit with NAND and NOR Gates Only
Autorzy:
Baranov, S.
Karatkevich, A.
Powiązania:
https://bibliotekanauki.pl/articles/963932.pdf
Data publikacji:
2018
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
logic synthesis
logic devices
VLSI
minimization
Opis:
In the paper we consider fast transformation of a multilevel and multioutput circuit with AND, OR and NOT gates into a functionally equivalent circuit with NAND and NOR gates. The task can be solved by replacing AND and OR gates by NAND or NOR gates, which requires in some cases introducing the additional inverters or splitting the gates. In the paper the quick approximation algorithms of the circuit transformation are proposed, minimizing number of the inverters. The presented algorithms allow transformation of any multilevel circuit into a circuit being a combination of NOR gates, NAND gates or both types of universal gates.
Źródło:
International Journal of Electronics and Telecommunications; 2018, 64, 3; 373-378
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Petri Net Based Specification in the Design of Logic Controllers with Exception Handling Mechanism
Autorzy:
Doligalski, M.
Adamski, M.
Powiązania:
https://bibliotekanauki.pl/articles/227254.pdf
Data publikacji:
2012
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
logic controller
dual specification
hierarchical Petri net
UML
state machine diagram
Opis:
Hierarchical Petri nets beside UML state machine diagrams, sequentional function charts (SFC) and hierarchical concurrent state machines are common solution for specification of logic controllers. These specification formats provide both concurrency and modeling on multi levels of abstraction (hierarchic approach). But only state machine diagrams supports exceptions handling in direct way. Program model presented in form of state machine diagram may be later transformed into a program in the SFC language or transformed in the Petri Net and implemented in the FPGA structure. Similarity between SFC language and Petri Nets give us lot of tools for analysis such control system. Article presents new approach for exceptions handling in hierarchical Petri nets as formal specification for logic controllers. Proposed method of specification can be used independently or as a part of dual specification (correlated state machine diagram and hierarchical configurable Petri Net).
Źródło:
International Journal of Electronics and Telecommunications; 2012, 58, 1; 43-48
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Graphene-based Current Mode Logic Circuits : a Simulation Study for an Emerging Technology
Autorzy:
Abdollahi, Hassan
Hooshmand, Reza
Owlia, Hadi
Powiązania:
https://bibliotekanauki.pl/articles/226818.pdf
Data publikacji:
2019
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
current mode logic (CML)
graphene
graphene FET
low-power design
Opis:
In this paper, the usage of graphene transistors is introduced to be a suitable solution for extending low power designs. Static and current mode logic (CML) styles on both nanoscale graphene and silicon FINFET technologies are compared. Results show that power in CML styles approximately are independent of frequency and the graphene-based CML (G-CML) designs are more power-efficient as the frequency and complexity increase. Compared to silicon-based CML (Si-CML) standard cells, there is 94% reduction in power consumption for G-CML counterparts. Furthermore, a G-CML 4-bit adder respectively offers 8.9 and 1.7 times less power and delay than the Si-CML adder.
Źródło:
International Journal of Electronics and Telecommunications; 2019, 65, 3; 381-388
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Structured Mapping of Petri Net States and Events for FPGA Implementations
Autorzy:
Tkacz, J.
Adamski, M.
Powiązania:
https://bibliotekanauki.pl/articles/227222.pdf
Data publikacji:
2013
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
configurable logic controllers
interpreted Petri net state space
local and global state encoding
hyperpgraph
logic design
Gentzen sequents
Petri net coloring
FPGA
VHDL
Opis:
The paper presents a new method of structured encoding of global internal states and events in Reconfigurable Logic Controllers, which are directly mapped into Field Programmable Gate Arrays (FPGA). Modular, concurrently decomposed, colored state machine is chosen as a intermediate model, before the mapping of Petri net into an array structure of dedicated but very flexible and reliable digital system. The initial textual specification in formal Gentzen logic serves both as a design description for a rapid prototyping, as well as formal model, suitable for detailed computer-based reasoning about optimized and synthesized logic controller, implemented in configurable hardware. Only the selected linear subset from general, universal propositional Gentzen Logic is necessary to deduce several properties of the net, such as relations of nonconcurrency among structurally ordered macroplaces. The goal of this paper is to present the design methodology for modeling and synthesis of discrete controllers using related Petri net theory, rule-based theory (mathematical logic), and VHDL.
Źródło:
International Journal of Electronics and Telecommunications; 2013, 59, 4; 331-339
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Graphical Method of Reversible Circuits Synthesis
Autorzy:
Skorupski, A.
Powiązania:
https://bibliotekanauki.pl/articles/226489.pdf
Data publikacji:
2017
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
reversible logic
reversible circuits
reversible gates
Toffoli gates
Opis:
This paper presents a new approach to designing reversible circuits. Reversible circuits can decrease energy dissipation theoretically to zero. This feature is a base to build quantum computers. The main problem of reversible logic is designing optimal reversible circuits i.e. circuits with minimal gates number implementing the given reversible function. There are many types of reversible gates. Most popular library is a set of three types of gates so called CNT (Control, NOT and Toffoli). The method presented in this paper is based only on the Toffoli gates. A graphical representation of the reversible function called s-maps is introduced in the paper. This representation allows to find optimal reversible circuits. The paper is organized as follows. Section 1 recalls basic concepts of reversible logic. In Section 2 a graphical representation of the reversible functions is presented. Section 3 describes the algorithm whereby all optimal solutions of the given function could be obtained.
Źródło:
International Journal of Electronics and Telecommunications; 2017, 63, 3; 235-240
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Conception of a Control Unit for Critical Systems
Autorzy:
Sałamaj, M.
Powiązania:
https://bibliotekanauki.pl/articles/226077.pdf
Data publikacji:
2013
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
safety logic microcontroller
critical systems
master-slave architecture
FPGA
conception
Opis:
The article regards critical systems precisely controlled by safety units. A new idea of safety logic microcontroller is proposed. It is built on the basis of the simplest mechanisms and technical solutions. This approach allowed to obtain a complex decision-making and control microsystem, in which the applied mechanisms and solutions increased its reliability. As a result, the proposed control unit proved to be a universal solution, which can be used in any critical system.
Źródło:
International Journal of Electronics and Telecommunications; 2013, 59, 4; 363-368
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Wyświetlanie 1-15 z 42

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