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Wyświetlanie 1-4 z 4
Tytuł:
Efficient FPGA Implementation of Recursive Least Square Adaptive Filter Using Non-Restoring Division Algorithm
Autorzy:
Thannoon, Harith H.
Hashim, Ivan A.
Powiązania:
https://bibliotekanauki.pl/articles/27311979.pdf
Data publikacji:
2023
Wydawca:
Polska Akademia Nauk. Czasopisma i Monografie PAN
Tematy:
Adaptive filter
RLS
AP
CORDIC
non-restoring
Opis:
In this paper, Recursive Least Square (RLS) and Affine Projection (AP) adaptive filters are designed using Xilinx System Generator and implemented on the Spartan6 xc6slx16- 2csg324 FPGA platform. FPGA platform utilizes the non-restoring division algorithm and the COordinate Rotation DIgital Computer (CORDIC) division algorithm to perform the division task of the RLS and AP adaptive filters. The Non-restoring division algorithm demonstrates efficient performance in terms of convergence speed and signal-to-noise ratio. In contrast, the CORDIC division algorithm requires 31 cycles for division initialization, whereas the non-restoring algorithm initializes division in just one cycle. To validate the effectiveness of the proposed filters, a set of ten ECG records from the BIT-MIT database is used to test their ability to remove Power Line Interference (PLI) noise from the ECG signal. The proposed adaptive filters are compared with various adaptive algorithms in terms of Signal-to-Noise Ratio (SNR), convergence speed, residual noise, steady-state Mean Square Error (MSE), and complexity.
Źródło:
International Journal of Electronics and Telecommunications; 2023, 69, 4; 811--817
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Design of a Predictive PID Controller Using Particle Swarm Optimization
Autorzy:
Mustafa, Norhaida
Hashim, Fazida Hanim
Powiązania:
https://bibliotekanauki.pl/articles/1844451.pdf
Data publikacji:
2020
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
proportional integral derivative controller
particle swarm optimization (PSO) algorithm
optimization
predictive PID
Opis:
The proportional-integral-derivative (PID) controller is widely used in various industrial applications such as process control, motor drives, magnetic and optical memory, automotive, flight control and instrumentation. PID tuning refers to the generation of PID parameters (Kp, Ki, Kd) to obtain the optimum fitness value for any system. The determination of the PID parameters is essential for any system that relies on it to function in a stable mode. This paper proposes a method in designing a predictive PID controller system using particle swarm optimization (PSO) algorithm for direct current (DC) motor application. Extensive numerical simulations have been done using the Mathwork’s Matlab simulation environment. In order to gain full benefits from the PSO algorithm, the PSO parameters such as inertia weight, iteration number, acceleration constant and particle number need to be carefully adjusted and determined. Therefore, the first investigation of this study is to present a comparative analysis between two important PSO parameters; inertia weight and number of iteration, to assist the predictive PID controller design. Simulation results show that inertia weight of 0.9 and iteration number 100 provide a good fitness achievement with low overshoot and fast rise and settling time. Next, a comparison between the performance of the DC motor with PID-PSO, with PID of gain 1, and without PID were also discussed. From the analysis, it can be concluded that by tuning the PID parameters using PSO method, the best gain in performance may be found. Finally, when comparing between the PID-PSO and its counterpart, the PI-PSO, the PID-PSO controller gives better performance in terms of robustness, low overshoot (0.005%), low minimum rise time (0.2806 seconds) and low settling time (0.4326 seconds).
Źródło:
International Journal of Electronics and Telecommunications; 2020, 66, 4; 737-743
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
A New Approach of an Error Detecting and Correcting Circuit by Arithmetic Logic Blocks
Autorzy:
Kavitha, S.
Hashim, Fazida Hanim
Kamal, Noorfazila
Powiązania:
https://bibliotekanauki.pl/articles/226549.pdf
Data publikacji:
2019
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
EDAC
ALU
speed
block reduction
power
slew rate
Opis:
This paper proposes a unique method of an error detection and correction (EDAC) circuit, carried out using arithmetic logic blocks. The modified logic blocks circuit and its auxiliary components are designed with Boolean and block reduction technique, which reduced one logic gate per block. The reduced logic circuits were simulated and designed using MATLAB Simulink, DSCH 2 CAD, and Microwind CAD tools. The modified, 2:1 multiplexer, demultiplexer, comparator, 1-bit adder, ALU, and error correction and detection circuit were simulated using MATLAB and Microwind. The EDAC circuit operates at a speed of 454.676 MHz and a slew rate of -2.00 which indicates excellence in high speed and low-area.
Źródło:
International Journal of Electronics and Telecommunications; 2019, 65, 2; 313-318
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Heart-rate Monitoring System Design and Analysis Using a Nios II Soft-core Processor
Autorzy:
Lim, C. K.
Jambek, A.B.
Hashim, U.
Powiązania:
https://bibliotekanauki.pl/articles/226033.pdf
Data publikacji:
2016
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
pulse sensor
PPG
heart rate
FPGA
Nios II
Opis:
The heart rate of a person is able to tell whether they are healthy. A heart-rate monitoring device is able to measure or record the heart rate of a person in real time, whether it is an electrocardiogram (ECG) or a photoplethysmogram (PPG). In this work, a microprocessor system loaded with a heart-rate monitoring algorithm is implemented. The microprocessor system is the Nios II processor system, which interfaces with an analogue-to-digital converter (ADC) and a pulse sensor. A beat-finding algorithm is used in the microprocessor system for heart rate measurement. An experiment is carried out to analyse the functionality of the microprocessor system loaded with the algorithm. The results show that the detected heart rate is in the range of the average human being’s heart rate. The signal flow within the microprocessor system is observed and analysed using SignalTap II from Quartus’ software. Based on a power analysis report, the proposed microprocessor system has a total power dissipation of around 218.26 mW.
Źródło:
International Journal of Electronics and Telecommunications; 2016, 62, 3; 283-288
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
    Wyświetlanie 1-4 z 4

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