- Tytuł:
- Hardware reduction for LUT-based mealy FSMs
- Autorzy:
-
Barkalov, A.
Titarenko, L.
Mielcarek, K. - Powiązania:
- https://bibliotekanauki.pl/articles/331362.pdf
- Data publikacji:
- 2018
- Wydawca:
- Uniwersytet Zielonogórski. Oficyna Wydawnicza
- Tematy:
-
Mealy FSM
FPGA
LUT
partition
encoding collection
output variables
automat Mealy'ego
zbiór kodowany
zmienne wyjściowe - Opis:
- A method is proposed targeting a decrease in the number of LUTs in circuits of FPGA-based Mealy FSMs. The method improves hardware consumption for Mealy FSMs with the encoding of collections of output variables. The approach is based on constructing a partition for the set of internal states. Each state has two codes. It diminishes the number of arguments in input memory functions. An example of synthesis is given, along with results of investigations. The method targets rather complex FSMs, having more than 15 states.
- Źródło:
-
International Journal of Applied Mathematics and Computer Science; 2018, 28, 3; 595-607
1641-876X
2083-8492 - Pojawia się w:
- International Journal of Applied Mathematics and Computer Science
- Dostawca treści:
- Biblioteka Nauki
Artykuł