Temat: tiling - Katalog OPAC zbiorów

Skocz do pozycji: 1.

Tytuł:: Hardware-aware tiling optimization for multi-core systems
Autorzy:: Adamski, D.
Jabłoński, G.
Powiązania:: https://bibliotekanauki.pl/articles/305250.pdf
Data publikacji:: 2017
Wydawca:: Akademia Górniczo-Hutnicza im. Stanisława Staszica w Krakowie. Wydawnictwo AGH
Tematy:: LLVM
tiling
data locality
polyhedral model
Opis:: This paper presents a proposal for a new tool that improves tiling efficiency for a given hardware architecture. This article also describes the correlation between the changing hardware architecture and methods of software optimization. The first chapter includes a short description of the change in hardware architecture that has occurred over the past ten years. The second chapter provides an overview of the tools that will be used in further research. The subsequent sections contain a description of the proposed hardware-aware tool for optimal tiling.
Źródło:: Computer Science; 2017, 18 (2); 145-162
1508-2806
2300-7036
Pojawia się w:: Computer Science
Dostawca treści:: Biblioteka Nauki

Artykuł

Skocz do pozycji: 2.

Tytuł:: Dynamic tile free scheduling for code with acyclic inter-tile dependence graphs
Autorzy:: Bielecki, W.
Skotnicki, P.
Powiązania:: https://bibliotekanauki.pl/articles/305409.pdf
Data publikacji:: 2017
Wydawca:: Akademia Górniczo-Hutnicza im. Stanisława Staszica w Krakowie. Wydawnictwo AGH
Tematy:: optimizing compilers
tiling
task scheduling
parallel computing
dependence graph
data locality
Opis:: Free scheduling is a task ordering technique under which instructions are executed as soon as their operands become available. Coarsening the grain of computations under the free schedule, by means of using groups of loop nest statement instances (tiles) in place of single statement instances, increases the locality of data accesses and reduces the number of synchronization events, and as a consequence improves program performance. The paper presents an approach for code generation that allows for the free schedule for tiles of arbitrarily nested affine loops at run-time. The scope of the applicability of the introduced algorithms is limited to tiled loop nests whose inter-tile dependence graphs are cycle-free. The approach is based on the polyhedral model. Results of experiments with the PolyBench benchmark suite, demonstrating significant tiled code speed-up, are discussed.
Źródło:: Computer Science; 2017, 18 (2); 195-216
1508-2806
2300-7036
Pojawia się w:: Computer Science
Dostawca treści:: Biblioteka Nauki

Artykuł

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