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    Wyświetlanie 1-6 z 6
    Tytuł:
    Realization of controlled NOT quantum gate via control of a two spin system
    Autorzy:
    Twardy, M.
    Olszewski, D.
    Powiązania:
    https://bibliotekanauki.pl/articles/201766.pdf
    Data publikacji:
    2013
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    quantum gates control
    CNOT gate
    quantum control
    Opis:
    Physical realization of controlled NOT quantum gate is addressed as a control problem for the system of two interacting spins. The control is carried out by magnetic pulses acting on the spins. The shapes of the appropriate magnetic pulses are computed.
    Źródło:
    Bulletin of the Polish Academy of Sciences. Technical Sciences; 2013, 61, 2; 379-390
    0239-7528
    Pojawia się w:
    Bulletin of the Polish Academy of Sciences. Technical Sciences
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Evaluation of gate drive circuit effect in cascode GaN-based applications
    Autorzy:
    Tan, Q. Y.
    Narayanan, E. M. S.
    Powiązania:
    https://bibliotekanauki.pl/articles/2173545.pdf
    Data publikacji:
    2021
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    cascode GaNFETs
    parasitics
    buck converter
    gate drive design
    kaskoda GaNFETs
    przetwornica
    pasożytnictwo
    projekt napędu bramy
    Opis:
    This work evaluates the influence of gate drive circuitry to cascode GaN device’s switching waveforms. This is done by comparing three PCBs using three double-pulse-test (DPT) with different gate driving loop design. Among important parasitic elements, source-side inductance shows a significant impact to gate-source voltage waveform. A simulation model based on experimental measurement of the cascode GaNFET used in this work is modified by author. The simulation model is implemented in a synchronous buck converter topology and hereby to assess the impact of gate driving loop of cascode GaN device in both continuous conduction mode (CCM) and critical conduction mode (CRM). Apart from simulation, a synchronous buck converter prototype is presented for experimental evaluation, which shows a 99.15% efficiency at 5A under soft-switching operation (CRM) with a 59ns dead-time.
    Źródło:
    Bulletin of the Polish Academy of Sciences. Technical Sciences; 2021, 69, 2; art. no. e136742
    0239-7528
    Pojawia się w:
    Bulletin of the Polish Academy of Sciences. Technical Sciences
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Evaluation of gate drive circuit effect in cascode GaN-based applications
    Autorzy:
    Tan, Q. Y.
    Narayanan, E. M. S.
    Powiązania:
    https://bibliotekanauki.pl/articles/2128152.pdf
    Data publikacji:
    2021
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    cascode GaNFETs
    parasitics
    buck converter
    gate drive design
    kaskoda GaNFETs
    przetwornica
    pasożytnictwo
    projekt napędu bramy
    Opis:
    This work evaluates the influence of gate drive circuitry to cascode GaN device’s switching waveforms. This is done by comparing three PCBs using three double-pulse-test (DPT) with different gate driving loop design. Among important parasitic elements, source-side inductance shows a significant impact to gate-source voltage waveform. A simulation model based on experimental measurement of the cascode GaNFET used in this work is modified by author. The simulation model is implemented in a synchronous buck converter topology and hereby to assess the impact of gate driving loop of cascode GaN device in both continuous conduction mode (CCM) and critical conduction mode (CRM). Apart from simulation, a synchronous buck converter prototype is presented for experimental evaluation, which shows a 99.15% efficiency at 5A under soft-switching operation (CRM) with a 59ns dead-time.
    Źródło:
    Bulletin of the Polish Academy of Sciences. Technical Sciences; 2021, 69, 2; e136742, 1--7
    0239-7528
    Pojawia się w:
    Bulletin of the Polish Academy of Sciences. Technical Sciences
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Compact nanosecond pulse generator based on IGBT and spark gap cooperation
    Autorzy:
    Achour, Y.
    Starzyński, J.
    Łasica, A.
    Powiązania:
    https://bibliotekanauki.pl/articles/202157.pdf
    Data publikacji:
    2020
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    pulsed power
    nanosecond generator
    Isolated Gate Bipolar Transistor (IGBT)
    spark gap
    avalanche mode Bipolar Junction Transistor
    Opis:
    The present paper describes a new architecture of a high-voltage solid-state pulse generator. This generator combines the two types of energy storage systems: inductive and capacitive, and consequently operates two types of switches: opening and closing. For the opening switch, an isolated gate bipolar transistor (IGBT) was chosen due to its interesting characteristics in terms of controllability and robustness. For the closing switch, two solutions were tested: spark-gap (SG) for a powerful low-cost solution and avalanche mode bipolar junction transistor (BJT) for a fully semiconductor structure. The new architecture has several advantages: simple structure and driving system, high and stable controllable repetition rate that can reach 1 kHz, short rising time of a few nanoseconds, high gain and efficiency, and low cost. The paper starts with the mathematical analysis of the generator operation followed by numerical simulation of the device. Finally add a comma the results were confirmed by the experimental test with a prototype generator. Additionally, a comparative study was carried out for the classical SG versus the avalanche mode BJT working as a closing switch.
    Źródło:
    Bulletin of the Polish Academy of Sciences. Technical Sciences; 2020, 68, 2; 377-388
    0239-7528
    Pojawia się w:
    Bulletin of the Polish Academy of Sciences. Technical Sciences
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Characteristic pulse detection method for fuzzy area
    Autorzy:
    Geng, Xin
    Du, Baoqiang
    Powiązania:
    https://bibliotekanauki.pl/articles/2173662.pdf
    Data publikacji:
    2022
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    frequency measurement
    group period
    phase coincidence fuzzy area
    measurement gate
    pomiar częstotliwości
    okres grupowy
    obszar rozmyty koincydencji faz
    bramka pomiarowa
    Opis:
    In order to achieve higher frequency measurement accuracy, this paper proposed a characteristic pulse detection method of fuzzy area based on the quantized phase processing method of different frequency groups. First, the fuzzy area of the group phase coincidence points continuously moved on the time axis after passing through delay elements. The moving distance, that is, the number of the delay elements was determined by the main clock cycle of the D flip-flop. After that, three groups of phase coincidence detection fuzzy areas in different positions were sent to the digital logic module to extract the edge pulses of the phase coincidence detection fuzzy area. The pulse width is determined by the difference between the clock cycles of the delay elements. The clock cycles of different delay units were adjusted to obtain nanosecond or even picosecond circuit detection resolution. Finally, the pulses generated at the edge of the phase coincidence fuzzy area are taken as the switching signal of the frequency signal counter, so the stability of the gate signal and the accuracy of the gate time measurement are improved. The experimental results show that frequency stability can reach the order of E–13/s. In addition, compared with the traditional measurement method, it is characterized by simple structure, low cost, low noises, and high measurement resolution.
    Źródło:
    Bulletin of the Polish Academy of Sciences. Technical Sciences; 2022, 70, 2; art. no. e140553
    0239-7528
    Pojawia się w:
    Bulletin of the Polish Academy of Sciences. Technical Sciences
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    FPGA implementation of logarithmic versions of Baum-Welch and Viterbi algorithms for reduced precision hidden Markov models
    Autorzy:
    Pietras, M.
    Klęsk, P.
    Powiązania:
    https://bibliotekanauki.pl/articles/201874.pdf
    Data publikacji:
    2017
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    hidden Markov models
    numerical stability
    Viterbi algorithm
    parallel architecture
    field-programmable gate array
    ukryte modele Markowa
    stabilność numeryczna
    Algorytm Viterbiego
    architektura równoległa
    Opis:
    This paper presents a programmable system-on-chip implementation to be used for acceleration of computations within hidden Markov models. The high level synthesis (HLS) and “divide-and-conquer” approaches are presented for parallelization of Baum-Welch and Viterbi algorithms. To avoid arithmetic underflows, all computations are performed within the logarithmic space. Additionally, in order to carry out computations efficiently – i.e. directly in an FPGA system or a processor cache – we postulate to reduce the floating-point representations of HMMs. We state and prove a lemma about the length of numerically unsafe sequences for such reduced precision models. Finally, special attention is devoted to the design of a multiple logarithm and exponent approximation unit (MLEAU). Using associative mapping, this unit allows for simultaneous conversions of multiple values and thereby compensates for computational efforts of logarithmic-space operations. Design evaluation reveals absolute stall delay occurring by multiple hardware conversions to logarithms and to exponents, and furthermore the experiments evaluation reveals HMMs computation boundaries related to their probabilities and floating-point representation. The performance differences at each stage of computation are summarized in performance comparison between hardware acceleration using MLEAU and typical software implementation on an ARM or Intel processor.
    Źródło:
    Bulletin of the Polish Academy of Sciences. Technical Sciences; 2017, 65, 6; 935-946
    0239-7528
    Pojawia się w:
    Bulletin of the Polish Academy of Sciences. Technical Sciences
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-6 z 6

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