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    Wyświetlanie 1-8 z 8
    Tytuł:
    On analog comparators for CMOS digital pixel applications. A comparative study
    Autorzy:
    Jendernalik, W.
    Powiązania:
    https://bibliotekanauki.pl/articles/200565.pdf
    Data publikacji:
    2016
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    CMOS image sensor
    CMOS digital pixel
    analog comparator
    fixed-pattern noise
    FPN
    CMOS
    matryca świałoczuła CMOS
    piksel cyfrowy
    komparator analogowy
    hałas ustalony
    Opis:
    Voltage comparator is the only - apart from the light-to-voltage converter - analog component in the digital CMOS pixel. In this work, the influence of the analog comparator nonidealities on the performance of the digital pixel has been investigated. In particular, two versions of the digital pixel have been designed in 0.35 μm CMOS technology, each using a different type of analog comparator. The properties of both versions have been compared. The first pixel utilizes a differential comparator with the increased size and improved electrical performance. The second structure is based on a very simple non-differential comparator with a reduced size and degraded performance. Theoretical analysis of the comparator nonideality effect on the quality of the image obtained from the digital pixel matrix as well as simulation results are provided.
    Źródło:
    Bulletin of the Polish Academy of Sciences. Technical Sciences; 2016, 64, 2; 271-278
    0239-7528
    Pojawia się w:
    Bulletin of the Polish Academy of Sciences. Technical Sciences
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Multiple output CMOS current amplifier
    Autorzy:
    Pankiewicz, B.
    Powiązania:
    https://bibliotekanauki.pl/articles/201141.pdf
    Data publikacji:
    2016
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    current amplifier
    current follower
    current mirror
    CMOS technology
    wzmacniacz prądowy
    prąd
    technologia CMOS
    Opis:
    In this paper the multiple output current amplifier basic cell is proposed. The triple output current mirror and current follower circuit are described in detail. The cell consists of a split nMOS differential pair and accompanying biasing current sources. It is suitable for low voltage operation and exhibits highly linear DC response. Through cell devices scaling, not only unity, but also any current gains are achievable. As examples, a current amplifier and bandpass biquad section designed in CMOS TSMC 90nm technology are presented. The current amplifier is powered from a 1.2V supply. MOS transistors scaling was chosen to obtain output gains equal to -2, 1 and 2. Simulated real gains are -1.941, 0.966 and 1.932 respectively. The 3dB passband obtained is above 20MHz, while current consumption is independent of input and output currents and is only 7.77μA. The bandpass biquad section utilises the previously presented amplifier, two capacitors and one resistor, and has a Q factor equal to 4 and pole frequency equal to 100 kHz.
    Źródło:
    Bulletin of the Polish Academy of Sciences. Technical Sciences; 2016, 64, 2; 301-306
    0239-7528
    Pojawia się w:
    Bulletin of the Polish Academy of Sciences. Technical Sciences
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Automatic tuning of a resonant circuit in wireless power supply systems for biomedical sensors
    Autorzy:
    Blakiewicz, G.
    Jakusz, J.
    Jendernalik, W.
    Szczepański, S.
    Powiązania:
    https://bibliotekanauki.pl/articles/201440.pdf
    Data publikacji:
    2016
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    CMOS circuits
    automatic tuning
    impedance matching
    resonant circuit
    układy CMOS
    tuning
    impedancja
    obwód rezonansowy
    Opis:
    In this paper, a tuning method of a resonant circuit suited for wireless powering of miniature endoscopic capsules is presented and discussed. The method allows for an automatic tuning of the resonant frequency and matching impedance of a full wave rectifier loading the resonant circuit. Thereby, the receiver tunes so as to obtain the highest power efficiency under given conditions of transmission. A prototype receiver for wireless power reception, fabricated in in AMS CMOS 0.35 μm technology, was used to verify correct operation of the proposed tuning. The prototype system produces a stable supply voltage, adjustable in the range of 1.2–1.8 V at a maximum output current of 100–67 mA, which is sufficient to power a typical endoscopic capsule.
    Źródło:
    Bulletin of the Polish Academy of Sciences. Technical Sciences; 2016, 64, 3; 641-646
    0239-7528
    Pojawia się w:
    Bulletin of the Polish Academy of Sciences. Technical Sciences
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Overheat protection circuit for high frequency processors
    Autorzy:
    Frankiewicz, M.
    Kos, A.
    Powiązania:
    https://bibliotekanauki.pl/articles/200992.pdf
    Data publikacji:
    2012
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    PTAT
    overheat
    CMOS
    VLSI
    full-custom design
    Opis:
    The paper describes design and structure of the overheat protection circuit based on the PTAT sensors. The digital core of the system is driven by a 3-bit information generated by the structure. As a result, behaviour of the core differs for each temperature. The circuit was designed in LF CMOS 0.15 ěm technology using full-custom technique. The presented paper focuses especially on the structure of the overheat protection circuit and simulations results of the functional blocks of the system. Layout and some parameters of the circuit are also considered.
    Źródło:
    Bulletin of the Polish Academy of Sciences. Technical Sciences; 2012, 60, 1; 55-59
    0239-7528
    Pojawia się w:
    Bulletin of the Polish Academy of Sciences. Technical Sciences
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Design of a nanoswitch in 130 nm CMOS technology for 2.4 GHz wireless terminals
    Autorzy:
    Bhuiyan, M. A.
    Reaz, M. B. I.
    Jalil, J.
    Rahman, L. F.
    Powiązania:
    https://bibliotekanauki.pl/articles/200508.pdf
    Data publikacji:
    2014
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    CMOS
    ISM band
    nanometer
    transceivers
    T/R switch
    wireless
    Opis:
    This paper proposes a transmit/receive (T/R) nanoswitch in 130 nm CMOS technology for 2.4 GHz ISM band transceivers. It exhibits 1.03-dB insertion loss, 27.57-dB isolation and a power handling capacity (P1 dB) of 36.2-dBm. It dissipates only 6.87 μW power for 1.8/0 V control voltages and is capable of switching in 416.61 ps. Besides insertion loss and isolation of the nanoswitch is found to vary by 0.1 dB and 0.9 dB, respectively for a temperature change of 125°C. Only the transistor W/L optimization and resistive body floating technique is used for such lucrative performances. Besides absence of bulky inductors and capacitors in the schematic circuit help to attain the smallest chip area of 0.0071 mm2 which is the lowest ever reported in this frequency band. Therefore, simplicity and low chip area of the circuit trim down the cost of fabrication without compromising the performance issue.
    Źródło:
    Bulletin of the Polish Academy of Sciences. Technical Sciences; 2014, 62, 2; 399-406
    0239-7528
    Pojawia się w:
    Bulletin of the Polish Academy of Sciences. Technical Sciences
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    CMOS realisation of analogue processor for early vision processing
    Autorzy:
    Jendernalik, W.
    Jakusz, J.
    Blakiewicz, G.
    Piotrowski, R.
    Szczepański, S.
    Powiązania:
    https://bibliotekanauki.pl/articles/202320.pdf
    Data publikacji:
    2011
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    CMOS imager
    analogue processor array
    smart sensor
    vision chip
    Opis:
    The architecture concept of a high-speed low-power analogue vision chip, which performs low-level real-time image algorithms is presented. The proof-of-concept prototype vision chip containing 32 �~ 32 photosensor array and 32 analogue processors is fabricated using a 0.35 mikrom CMOS technology. The prototype can be configured to register and process images with very high speed, reaching 2000 frames per second, or achieve very low power consumption, several mikroW. Finally, the experimental results are presented and discussed.
    Źródło:
    Bulletin of the Polish Academy of Sciences. Technical Sciences; 2011, 59, 2; 141-147
    0239-7528
    Pojawia się w:
    Bulletin of the Polish Academy of Sciences. Technical Sciences
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    CMOS implementation of an analogue median filter for image processing in real time
    Autorzy:
    Jendernalik, W.
    Jakusz, J.
    Blakiewicz, G.
    Szczepański, S.
    Powiązania:
    https://bibliotekanauki.pl/articles/202129.pdf
    Data publikacji:
    2013
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    analogue CMOS circuits
    early vision processing
    median filter
    low-power
    Opis:
    An analogue median filter, realised in a 0.35 μm CMOS technology, is presented in this paper. The key advantages of the filter are: high speed of image processing (50 frames per second), low-power operation (below 1.25 mW under 3.3 V supply) and relatively high accuracy of signal processing. The presented filter is a part of an integrated circuit for image processing (a vision chip), containing: a photo-sensor matrix, a set of analogue pre-processors, and interface circuits. The analysis of the main parameters of the considered median filter is presented. The discussion of important limitations in the operation of the filter due to the restrictions imposed by CMOS technology is also presented.
    Źródło:
    Bulletin of the Polish Academy of Sciences. Technical Sciences; 2013, 61, 3; 725-730
    0239-7528
    Pojawia się w:
    Bulletin of the Polish Academy of Sciences. Technical Sciences
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Technique to improve CMRR at high frequencies in CMOS OTA-C filters
    Autorzy:
    Blakiewicz, G.
    Powiązania:
    https://bibliotekanauki.pl/articles/200504.pdf
    Data publikacji:
    2013
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Tematy:
    common-mode rejection ratio
    CMRR
    CMOS
    OTA
    differential pair
    OTA-C filters
    component mismatch
    Opis:
    In this paper a technique to improve the common-mode rejection ratio (CMRR) at high frequencies in the OTA-C filters is proposed. The technique is applicable to most OTA-C filters using CMOS operational transconductance amplifiers (OTA) based on differential pairs. The presented analysis shows that a significant broadening of CMRR bandwidth can be achieved by using a differential pair with the bodies of transistors connected to AC ground, instead of using a pair with the bodies connected to the sources. The key advantages of the technique are: no increase in power consumption (except for an optional tuning circuit), a small increase of a chip area, a slight modification of the original filter. The simulation results for exemplary OTAs and a low-pass filter, designed in a 0.35 μm CMOS process, show the possibility of broadening the CMRR bandwidth several times.
    Źródło:
    Bulletin of the Polish Academy of Sciences. Technical Sciences; 2013, 61, 3; 697-703
    0239-7528
    Pojawia się w:
    Bulletin of the Polish Academy of Sciences. Technical Sciences
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-8 z 8

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