Temat: symbolic controller synthesis - Katalog OPAC zbiorów

Skocz do pozycji: 1.

Tytuł:: On distributed symbolic control of interconnected systems under persistency specifications
Autorzy:: Apaza-Perez, W. Alejandro
Combastel, Christophe
Zolghadri, Ali
Powiązania:: https://bibliotekanauki.pl/articles/1838152.pdf
Data publikacji:: 2020
Wydawca:: Uniwersytet Zielonogórski. Oficyna Wydawnicza
Tematy:: symbolic controller synthesis
distributed controller
interconnected system
synteza kontrolera
rozproszony system sterowania
system połączony
Opis:: This paper presents an abstraction-based technique to solve the problem of distributed controller design enforcing persistency specifications for interconnected systems. For each subsystem, controller synthesis is based on local distributed sensor information from other subsystems. An effective method is presented for quantification of such partial information in an abstraction in terms of level sets of Lyapunov-like ranking functions. The results are illustrated on a laboratory hydraulic system.
Źródło:: International Journal of Applied Mathematics and Computer Science; 2020, 30, 4; 629-639
1641-876X
2083-8492
Pojawia się w:: International Journal of Applied Mathematics and Computer Science
Dostawca treści:: Biblioteka Nauki

Artykuł

Skocz do pozycji: 2.

Tytuł:: Power-aware scheduling of data-flow hardware circuits with symbolic control
Autorzy:: Özbaltan, Mete
Berthier, Nicolas
Powiązania:: https://bibliotekanauki.pl/articles/1409402.pdf
Data publikacji:: 2021
Wydawca:: Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:: symbolic discrete controller synthesis
digital synchronous circuits
power efficiency
Opis:: We devise a tool-supported framework for achieving power-efficiency of data-flow hardware circuits. Our approach relies on formal control techniques, where the goal is to compute a strategy that can be used to drive a given model so that it satisfies a set of control objectives. More specifically, we give an algorithm that derives abstract behavioral models directly in a symbolic form from original designs described at Register-transfer Level using a Hardware Description Language, and for formulating suitable scheduling constraints and power-efficiency objectives. We show how a resulting strategy can be translated into a piece of synchronous circuit that, when paired with the original design, ensures the aforementioned objectives. We illustrate and validate our approach experimentally using various hardware designs and objectives.
Źródło:: Archives of Control Sciences; 2021, 31, 2; 431-446
1230-2384
Pojawia się w:: Archives of Control Sciences
Dostawca treści:: Biblioteka Nauki

Artykuł

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