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    Wyświetlanie 1-5 z 5
    Tytuł:
    An ANN-based scalable hashing algorithm for computational clouds with schedulers
    Autorzy:
    Tchórzewski, Jacek
    Jakóbik, Agnieszka
    Iacono, Mauro
    Powiązania:
    https://bibliotekanauki.pl/articles/2055176.pdf
    Data publikacji:
    2021
    Wydawca:
    Uniwersytet Zielonogórski. Oficyna Wydawnicza
    Tematy:
    hashing algorithm
    artificial neural network
    scalable cryptography algorithm
    computational cloud
    task scheduler
    algorytm haszowania
    sztuczna sieć neuronowa
    algorytm kryptograficzny
    chmura obliczeniowa
    Opis:
    The significant benefits of cloud computing (CC) resulted in an explosion of their usage in the last several years. From the security perspective, CC systems have to offer solutions that fulfil international standards and regulations. In this paper, we propose a model for a hash function having a scalable output. The model is based on an artificial neural network trained to mimic the chaotic behaviour of the Mackey–Glass time series. This hashing method can be used for data integrity checking and digital signature generation. It enables constructing cryptographic services according to the user requirements and time constraints due to scalable output. Extensive simulation experiments are conduced to prove its cryptographic strength, including three tests: a bit prediction test, a series test, and a Hamming distance test. Additionally, flexible hashing function performance tests are run using the CloudSim simulator mimicking a cloud with a global scheduler to investigate the possibility of idle time consumption of virtual machines that may be spent on the scalable hashing protocol. The results obtained show that the proposed hashing method can be used for building light cryptographic protocols. It also enables incorporating the integrity checking algorithm that lowers the idle time of virtual machines during batch task processing.
    Źródło:
    International Journal of Applied Mathematics and Computer Science; 2021, 31, 4; 697--712
    1641-876X
    2083-8492
    Pojawia się w:
    International Journal of Applied Mathematics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Skalowalny algorytm estymacji ruchu dla systemów rozproszonych
    A scalable motion estimation algorithm for distributed systems
    Autorzy:
    Konieczny, J.
    Łuczak, A.
    Powiązania:
    https://bibliotekanauki.pl/articles/154045.pdf
    Data publikacji:
    2009
    Wydawca:
    Stowarzyszenie Inżynierów i Techników Mechaników Polskich
    Tematy:
    algorytm skalowalny
    estymacja ruchu
    systemy rozproszone
    przetwarzanie w czasie rzeczywistym
    scalable algorithm
    motion estimation
    distributed systems
    real-time processing
    Opis:
    W pracy zaprezentowano autorski algorytm umożliwiający realizację procesu estymacji ruchu w czasie rzeczywistym przy wykorzystaniu systemów rozproszonych. Jest to algorytm należący do grupy tzw. szybkich algorytmów estymacji ruchu i umożliwia estymację ruchu z rozdzielczością poniżej jednego okresu próbkowania. Zaproponowany algorytm jest skalowalny i posiada budowę modułową, umożliwia elastyczne dostosowanie do rozmiaru układu oraz udostępnia mechanizm kontroli liczby cykli zegara niezbędnych do estymacji ruchu. W rezultacie możliwe jest dostosowanie częstotliwości zegara do możliwości układu przy zapewnieniu przetwarzania w czasie rzeczywistym.
    In this paper a novel scalable algorithm for real-time motion estimation dedicated for distributed systems is presented. The proposed algorithm has modular structure and provides ability to flexibly adjust the global clock-rate required for real-time processing. This is achieved using hierarchical structure of the algorithm, which assumes division of the whole motion estimation process into independent processing stages (Figs. 1, 3, 4) and introducing special mechanism for controlling the allowed number of computation cycles. The algorithm modularity provides additional profits like ability to choose various methods for each processing stage independently and scalability of the circuit structure resulting in more efficient hardware implementation. Flexible clock-rate adjustment enables real-time processing with various types of computational platforms, with special regards to distributed systems consisting of many low-performance units. An example of scalable performance of the algorithm in distributed systems is presented. In order to increase the image resolution in real-time processing the processed image is shared between many processing units (Fig. 5). An exemplary system used for evaluation was created using Digilent "Starter Boards" with Xilinx Spartan-3 XC3S1000 FPGA circuits connected with NOC (Network On Chip) (Fig. 6). In the presented implementation six Spartan-3 circuits were able to estimate motion vectors with half-pel accuracy in real-time for HD resolution (1920x1080) video sequence with 25 frames per second.
    Źródło:
    Pomiary Automatyka Kontrola; 2009, R. 55, nr 8, 8; 684-686
    0032-4140
    Pojawia się w:
    Pomiary Automatyka Kontrola
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Audio Compression using a Modified Vector Quantization algorithm for Mastering Applications
    Autorzy:
    Prince, Shajin
    D, Bini
    Kirubaraj, Alfred A.
    Immanuel, Samson J.
    M, Surya
    Powiązania:
    https://bibliotekanauki.pl/articles/27311916.pdf
    Data publikacji:
    2023
    Wydawca:
    Polska Akademia Nauk. Czasopisma i Monografie PAN
    Tematy:
    vector quantization
    scalable
    perceptual coder
    audio mastering
    bit stream
    Opis:
    Audio data compression is used to reduce the transmission bandwidth and storage requirements of audio data. It is the second stage in the audio mastering process with audio equalization being the first stage. Compression algorithms such as BSAC, MP3 and AAC are used as standards in this paper. The challenge faced in audio compression is compressing the signal at low bit rates. The previous algorithms which work well at low bit rates cannot be dominant at higher bit rates and vice-versa. This paper proposes an altered form of vector quantization algorithm which produces a scalable bit stream which has a number of fine layers of audio fidelity. This modified form of the vector quantization algorithm is used to generate a perceptually audio coder which is scalable and uses the quantization and encoding stages which are responsible for the psychoacoustic and arithmetical terminations that are actually detached as practically all the data detached during the prediction phases at the encoder side is supplemented towards the audio signal at decoder stage. Therefore, clearly the quantization phase which is modified to produce a bit stream which is scalable. This modified algorithm works well at both lower and higher bit rates. Subjective evaluations were done by audio professionals using the MUSHRA test and the mean normalized scores at various bit rates was noted and compared with the previous algorithms.
    Źródło:
    International Journal of Electronics and Telecommunications; 2023, 69, 2; 287--292
    2300-1933
    Pojawia się w:
    International Journal of Electronics and Telecommunications
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Torus-connected cycles: A simple and scalable topology for interconnection networks
    Autorzy:
    Bossard, A.
    Kaneko, K.
    Powiązania:
    https://bibliotekanauki.pl/articles/330544.pdf
    Data publikacji:
    2015
    Wydawca:
    Uniwersytet Zielonogórski. Oficyna Wydawnicza
    Tematy:
    algorithm
    routing
    Hamiltonian method
    supercomputer
    parallel
    algorytm
    metoda Hamiltonowska
    superkomputer
    system równoległy
    Opis:
    Supercomputers are today made up of hundreds of thousands of nodes. The interconnection network is responsible for connecting all these nodes to each other. Different interconnection networks have been proposed; high performance topologies have been introduced as a replacement for the conventional topologies of recent decades. A high order, a low degree and a small diameter are the usual properties aimed for by such topologies. However, this is not sufficient to lead to actual hardware implementations. Network scalability and topology simplicity are two critical parameters, and they are two of the reasons why modern supercomputers are often based on torus interconnection networks (e.g., Fujitsu K, IBM Sequoia). In this paper we first describe a new topology, torus-connected cycles (TCCs), realizing a combination of a torus and a ring, thus retaining interesting properties of torus networks in addition to those of hierarchical interconnection networks (HINs). Then, we formally establish the diameter of a TCC, and deduce a point-to-point routing algorithm. Next, we propose routing algorithms solving the Hamiltonian cycle problem, and, in a two dimensional TCC, the Hamiltonian path one. Correctness and complexities are formally proved. The proposed algorithms are time-optimal.
    Źródło:
    International Journal of Applied Mathematics and Computer Science; 2015, 25, 4; 723-735
    1641-876X
    2083-8492
    Pojawia się w:
    International Journal of Applied Mathematics and Computer Science
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Administration-and communication-aware IP core mapping in scalable multiprocessor system-on-chips via evolutionary computing
    Autorzy:
    Guderian, F.
    Schaffer, R.
    Fettweis, G.
    Powiązania:
    https://bibliotekanauki.pl/articles/91539.pdf
    Data publikacji:
    2012
    Wydawca:
    Społeczna Akademia Nauk w Łodzi. Polskie Towarzystwo Sieci Neuronowych
    Tematy:
    intellectual property
    IP
    IP core
    mapping
    system-on-chips
    mixed-integer linear programming
    MILP
    genetic algorithm
    GA
    administration
    communication
    Opis:
    In this paper, an efficient mapping of intellectual property (IP) cores onto a scalable multiprocessor system-on-chip with a k-ary 2-mesh network-on-chip is performed. The approach is to place more affine IP cores closer to each other reducing the number of traversed routers. Affinity describes the pairwise relationship between the IP cores quantified by an amount of exchanged communication or administration data. A genetic algorithm (GA) and a mixed-integer linear programming (MILP) solution use the affinity values in order to optimize the IP core mappings. The GA generates results faster and with a satisfactory quality relative to MILP. Realistic benchmark results demonstrate that a tradeoff between administration and communication affinity significantly improves application performance.
    Źródło:
    Journal of Artificial Intelligence and Soft Computing Research; 2012, 2, 2; 133-146
    2083-2567
    2449-6499
    Pojawia się w:
    Journal of Artificial Intelligence and Soft Computing Research
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-5 z 5

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