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Wyszukujesz frazę "analog CMOS circuits" wg kryterium: Temat


Wyświetlanie 1-8 z 8
Tytuł:
Analogue CMOS ASICs in image processing systems
Autorzy:
Jendernalik, W.
Blakiewicz, G.
Handkiewicz, A.
Melosik, M.
Powiązania:
https://bibliotekanauki.pl/articles/221661.pdf
Data publikacji:
2013
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
analog CMOS circuits
early vision processing
switched current filters
Opis:
In this paper a survey of analog application specific integrated circuits (ASICs) for low-level image processing, called vision chips, is presented. Due to the specific requirements, the vision chips are designed using different architectures best suited to their functions. The main types of the vision chip architectures and their properties are presented and characterized on selected examples of prototype integrated circuits (ICs) fabricated in complementary metal oxide semiconductor (CMOS) technologies. While discussing the vision chip realizations the importance of low-cost, low-power solutions is highlighted, which are increasingly being used in intelligent consumer equipment. Thanks to the great development of the automated design environments and fabrication methods, new, so far unknown applications of the vision chips become possible, as for example disposable endoscopy capsules for photographing the human gastrointestinal tract for the purposes of medical diagnosis.
Źródło:
Metrology and Measurement Systems; 2013, 20, 4; 613-622
0860-8229
Pojawia się w:
Metrology and Measurement Systems
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Fast Determination of Similarity Between Two Vectors by Means of Analog CMOS Technique
Autorzy:
Wojtyna, R.
Powiązania:
https://bibliotekanauki.pl/articles/226703.pdf
Data publikacji:
2010
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
hardware signal processing
fast Euclidean distance calculation
analog CMOS circuits
Opis:
In this paper, an analog approach to determining a resemblance between two multidimensional vectors is proposed. As the resemblance measure, Euclidean distance is used. The main advantage of the presented method is a very high speed of the Euclidean-distance-measure calculations. The achieved high speed results from the fact that most of arithmetic operations needed to realize the calculations are carried out in parallel. This concerns the required operations of squaring a difference of two corresponding components of the compared vectors. Operating in a transconductane mode (voltage difference squaring transconductors) and a current mode (output square-root extracting circuit), our CMOS circuit is power saving. Its low-power operation results from the fact that sub-circuits of our calculator responsible for the squaring operations (a great number of them in case of large multidimensional vectors) consume no power in the absence of input signals. This takes place when corresponding components of the compared vectors are both equal to zero. The circuit also consumes a reasonably low amount of energy when processing (comparing) a different from zero input data (corresponding vector components). A simplified description of the applied differential squaring transconductors as well as the output current-mode square-root extraction circuit is given and a problem of good cooperation between them is discussed and proper solutions indicated. SPICE simulation results are shown to be in a good agreement with the theory presented.
Źródło:
International Journal of Electronics and Telecommunications; 2010, 56, 4; 417-422
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Cascode amplifiers with low-gain variability and gain enhancement using a body-biasing technique
Autorzy:
Pereira, N
Oliveira, L. B.
Goes, J.
Oliveira, J. P.
Powiązania:
https://bibliotekanauki.pl/articles/398063.pdf
Data publikacji:
2013
Wydawca:
Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:
amplifier
body-biasing
cascode
CMOS analog circuits
PVT compensation
wzmacniacz
kaskoda
układy analogowe CMOS
kompensacja PVT
Opis:
This paper presents a simple circuit technique to reduce gain variability with PVT variations in cascode amplifiers using a body-biasing scheme, while enhancing the overall gain of the amplifier. Simulation results of a standard telescopic-cascode amplifier, in two different nanoscale CMOS technologies (130 nm and 65 nm) show that the proposed compensated circuit amplifier exhibits a (DC) gain variability smaller (below ± 0.5 dB) than the original (uncompensated) circuit, while reaching a gain enhancement of about 3 dB. The required auxiliary biasing circuit dissipates around 5% of the main amplifier circuit.
Źródło:
International Journal of Microelectronics and Computer Science; 2013, 4, 3; 98-102
2080-8755
2353-9607
Pojawia się w:
International Journal of Microelectronics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Fully Analytical Characterization of the Series Inductance of Tapered Integrated Inductors
Autorzy:
Passos, F.
Fino, M. H.
Moreno, E. R.
Powiązania:
https://bibliotekanauki.pl/articles/226450.pdf
Data publikacji:
2014
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
inductor design
variable width integrated spiral inductor
integrated spiral inductor
CMOS analog circuits
IC designing
RF IC design
Opis:
In this paper a general method for the determination of the series inductance of polygonal tapered inductor s is presented. The value obtained can be integrated into any integrated inductor lumped element model, thus granting the overall characterization of the device and the evaluation of performance parameters such as the quality factor or the resonance frequency. In this work, the inductor is divided into several segments and the corresponding self and mutual inductances are calculated. In the end, results obtained for several working examples are compared against electromagnetic (EM) simulations are performed in order to check the validity of the model for square, hexagonal, octagonal and tapered inductors. The proposed method depends exclusively on the geometric characteristics of the inductor as well as the technological parameters. This allows its straight forward application to any inductor shape or technology.
Źródło:
International Journal of Electronics and Telecommunications; 2014, 60, 1; 73-77
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Versatile low-output-resistance low-voltage current-to-voltage analog converter
Autorzy:
Wojtyna, R.
Powiązania:
https://bibliotekanauki.pl/articles/397867.pdf
Data publikacji:
2016
Wydawca:
Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:
CMOS analog integrated circuits
low-voltage signal processing
current to voltage conversion
transresistor
układy analogowe CMOS
układy scalone CMOS
przetwarzanie sygnałów
konwersja prąd na napięcie
transrezystor
Opis:
The paper presents a simple low-voltage transresistor attractive for on-chip analog-signal-processing. The proposed circuit offers not only an almost rail-to-rail operation and quite good linearity of DC transfer characteristic but also reasonably low value of its output resistance. This enables a voltage mode operation even if the transresistor is loaded by a not necessarily very high loading resistance. The obtained result is due to adding to the transresistor-input-stage a simple rail-to-rail voltage follower. The presented solution is an original proposal of the author. Input stage of the transresistor is built of only 4 MOS transistors and creates a simple quasi-linear current-to-voltage convertor. Output stage of it is built of 9 MOS transistors, plays a role of a very precise atypical voltage follower. In respect of simplicity and headroom, the proposed follower is better than conventional OA-based voltage followers. Preliminary simulation results are in a good agreement with the theory presented.
Źródło:
International Journal of Microelectronics and Computer Science; 2016, 7, 2; 73-78
2080-8755
2353-9607
Pojawia się w:
International Journal of Microelectronics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Fast Low Voltage Analog Four-Quadrant Multipliers Based on CMOS Inverters
Autorzy:
Machowski, W.
Kuta, S.
Jasielski, J.
Kołodziejski, W.
Powiązania:
https://bibliotekanauki.pl/articles/226683.pdf
Data publikacji:
2010
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
analog VLSI
four-quadrant multiplier
CMOS circuits
low voltage circuits
Opis:
The paper presents quarter-square analog four-quadrant multipliers, based on proprietary architecture using four CMOS inverters. The most important upgrade on already published own circuit implementation is the use of the same inverter "core" of the circuit with completely redesigned auxiliary and steering blocks. Two variants of new driving peripherals are considered: one with differential pair, the second with CMOS inverters. The proposed circuit solutions are suitable for RF applications in communication systems due to simple architecture comprising building blocks with RF CMOS transistors having sufficiently large biasing currents. Postlayout simulation results done on the basis of 180nm CMOS UMC Foundry Design Kit are also presented.
Źródło:
International Journal of Electronics and Telecommunications; 2010, 56, 4; 381-386
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
The Impact of Noise and Mismatch on SAR ADCs and a Calibratable Capacitance Array Based Approach for High Resolutions
Autorzy:
Mueller, J. H.
Strache, S.
Busch, L.
Wunderlich, R.
Heinen, S.
Powiązania:
https://bibliotekanauki.pl/articles/226396.pdf
Data publikacji:
2013
Wydawca:
Polska Akademia Nauk. Czytelnia Czasopism PAN
Tematy:
analog-digital conversion
analog-digital integrated circuits
calibration
CMOS integrated circuits
mathematical model
MATLAB
mixed analog digital integrated circuits
noise
numerical simulation
prediction methods
Opis:
This paper describes widely used capacitor structures for charge-redistribution (CR) successive approximation register (SAR) based analog-to-digital converters (ADCs) and analyzes their linearity limitations due to kT/C noise, mismatch and parasitics. Results of mathematical considerations and statistical simulations are presented which show that most widespread dimensioning rules are overcritical. For high-resolution CR SAR ADCs in current CMOS technologies, matching of the capacitors, influenced by local mismatch and parasitics, is a limiting factor. For high-resolution medium-speed CR SAR ADCs, a novel capacitance array based approach using in-field calibration is proposed. This architecture promises a high resolution with small unit capacitances and without expensive factory calibration as laser trimming.
Źródło:
International Journal of Electronics and Telecommunications; 2013, 59, 2; 161-167
2300-1933
Pojawia się w:
International Journal of Electronics and Telecommunications
Dostawca treści:
Biblioteka Nauki
Artykuł
Tytuł:
Power-saving voltage-to-current conversion with the use of CMOS differential amplifier
Autorzy:
Wojtyna, R.
Powiązania:
https://bibliotekanauki.pl/articles/398104.pdf
Data publikacji:
2015
Wydawca:
Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Tematy:
analog signal processing
differential amplifier
CMOS electronics
low-power analog circuits
analogowe przetwarzanie sygnałów
wzmacniacz różnicowy
CMOS
obwody niskiego napięcia
Opis:
Differential amplifiers are well known as input stage preamplifiers. This is because they exhibit the ability to reduce unwanted common-mode effects considerably. As a consequence, both noise and input signal of the amplifier can have low values. Proper operation of differential amplifiers is possible when implemented in chip form. For typical use of such CMOS amplifiers, input signals are delivered to differential-pair gate-terminals while tail terminal is used to ensure the required bias of the pair. The paper shows that the roles of gates and tail terminal can be changed. In other words, the tail current can be used as input signal while the gate ones as voltages controlling the amplifier gain. This enables to combine the achievable low noise with power efficient operation of the circuit. Necessary conditions for that are discussed in this paper. Suitability of atypically used differential amplifiers for voltage-to-current conversion is explained. Two examples of CMOS circuits implementing power economic conversion of this type are presented.
Źródło:
International Journal of Microelectronics and Computer Science; 2015, 6, 3; 96-101
2080-8755
2353-9607
Pojawia się w:
International Journal of Microelectronics and Computer Science
Dostawca treści:
Biblioteka Nauki
Artykuł
    Wyświetlanie 1-8 z 8

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