Low-delay dispersion comparator for level crossing analog to digital converters

This paper presents a cost-effective technique for reducing the delay dispersion of the conventional comparator for level-crossing Analog-to -Digital Converters. Only three transistors, representing a variable driving-current block (VDCB), have been added to the conventional comparator circuit. The VDCB attempts to control the charging behavior of the difference amplifier’ output node. The added block incurs small area overhead and low power consumption compared with the previous works. The proposed circuit has been implemented in MOSIS 130nm technology. The simulation results indicate that the overdrive-related propagation delay dispersion of the proposed technique is reduced to 23% of its counterpart in the conventional comparator. The active area of the proposed circuit is 140.2 μm2 and the power consumption is 227μW at 200MHz. For the sake of scalability check, the proposed circuit is also designed and simulated using 45nm technology. The simulation results came in the same direction, which implies the scalability of the proposed circuit.