Experimental study of snubber circuit design for SiC power MOSFET devices

In this paper a design process of snubber circuit for DC\DC converter is presented. Computer simulation and experimental tests were carried out. Due to the presence of parasitic LC (inductance and capacitance) circuit in the power stage, it is necessary to use an additional snubber circuit for voltage overshoot and oscillations reduction. A simulation model of the converter with parasitic circuit was designed. Six topologies of snubber circuits (C, single C, RC, single RC, RCD, single RCD) were investigated in simulation tests. Simulation model of the proposed system has been investigated in Matlab/Simulink/PLECS environment. Input signal parameters like voltage overshoot, rise time, fall time were compared for considered snubber circuits. Experimental tests were carried out for the best simulation results. It confirm the proper choice of snubber circuit.