Układ SoC - FPGA do detekcji twarzy w obrazach cyfrowych

W artykule przedstawiono wyniki badań dotyczących sprzętowej implementacji algorytmu detekcji twarzy w obrazach cyfrowych z wykorzystaniem układów programowalnych FPGA (Xilinx). Przeprowadzono symulację algorytmu w środowisku PC - Matlab. Przebadany wstępnie algorytm zaimplementowano w układzie FPGA Virtex-4. Wykonano badania eksperymentalne, w których porównano szybkość działania algorytmu w wersji programowej i sprzętowej oraz określono zajętość zasobów układu FPGA.

In this paper there are presented recent results of the authors' work on implementation of face detection algorithms in digital images based on FPGA technology from Xilinx. There was considered a number of existing face detection methods, described in papers [1-3] to find out which one is the best for implementation in a single FPGA device. Then the authors proposed a modified algorithm for face detection that was tested using PC - MATLAB environment. The results of software simulations were used for appropriate adjusting of some essential parameters, according to the requirements of FPGA implementation (the basic limitation is a total number of FPGA resources). The main results of simulations are shown in Tab. 1. The final version of the algorithm was im-plemented in a Virtex-4 FPGA device and tested using a set of example digital images. An important advantage of the proposed SoC for face detection is its speed (2-4 times higher than that for software implementation, as it is shown in Tab. 2). Furthermore, this speed does not depend on the window size used in image analysis. There was also reported the final utilization of FPGA resources (Tab. 3). The experimental results obtained from laboratory tests of the proposed face detection algorithm implemented in a single FPGA device show that the hardware approach to face detection problem has important advantages: high speed, flexibility and relatively low requirements on the total number of FPGA resources.