Synteza behawioralna sterowników rekonfigurowalnych na podstawie modelu maszyny stanowej UML

W pracy przedstawiono nową metodę projektowania sterowników logicznych realizowanych w sposób układowy w strukturach FPGA z wykorzystaniem języka Verilog. Modelem behawioralnym programu sterownika jest diagram maszyny stanowej UML 2.1.2. Formalnym modelem struktu-ralnym jest hierarchiczna sieć współpracujących ze sobą automatów cyfrowych. Wynikiem jest modularny opis modelowanego systemu w języku opisu sprzętu Verilog. Taka specyfikacja tekstowa może być następnie poddana symulacji i syntezie w zewnętrznych systemach.

The Unified Modeling Language (UML) is a language for specifying, visualizing, constructing, and documenting artifacts of software systems [9], as well as for business modelling and other non-software, for example reactive, systems [1, 8, 10]. The UML represents a collection of the best engineering practices that have proven successful in modelling large and complex systems [14]. The current version of the language is 2.1.2 [6]. One of the UML diagrams is a state machine diagram that defines a set of concepts that can be used for modelling discrete behavior through finite state transition systems. The paper presents a new design method for reconfigurable logic controllers implemented as digital circuit in Field Programmable Gate Arrays (FPGA) by means of hardware description language Verilog. The UML state machine diagram is used as an initial behavioural model [5]. It is worth mentioning that state machine diagrams support various features of the modelling systems such as hierarchy and orthogonality [12]. Figure 2 shows a state machine diagram for the exemplary model of two trolleys control process (Fig. 1) [2]. The formal structured design model is based on the hierarchical network of collaborated Finite State Machines [3, 15]. The specification in Verilog can be simulated and synthesized in professional tools, e.g. Active HDL or Xilinx ISE. To verify presented method a special CAD system UML-XML2Verilog was designed. This system allows automating the translation process from UML diagrams (described in XML) to behavioural, synthesized specification in Verilog. As for future research, the use of other diagrams from UML is going to be investigated.