The Effect of Phosphorus Incorporation into $SiO_2$/4H-SiC (0001) Interface on Electrophysical Properties of MOS Structure

This paper describes the influence of phosphorus incorporation into $SiO_2$/4H-SiC system. The main scope is an analysis of the slow responding trap states (near interface traps) since the influence of phosphorus technology on fast traps has already been investigated by numerous research groups. Two different phosphorus incorporation methods were incorporated - the diffusion-based process of $POCl_3$ annealing and ion implantation. We have shown that regardless of method used a new distinct near interface trap center can be found located approximately at $E_{V}$ + 3.0 eV. This trap can be related to the incorporated phosphorus amount as shown through secondary ion mass spectroscopy measurements.